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Revert "[X86][APX] Add pattern for zext(X86setcc ..) -> SETZUCCr (#170806)" #172192
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…m#170806)" This reverts commit 2612dc9 but keeps `Predicates = [HasNDD]` removed. There are two issues identified related to the change. One is INSERT_SUBREG cannot guarantee source and dest to be the same register. It mostly happens on O0. The other one is zero_extend is not a chain node, as a result, we will lose the chain for SETZUCCr.
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@llvm/pr-subscribers-backend-x86 Author: Phoebe Wang (phoebewang) ChangesThis reverts commit 2612dc9 but keeps There are two issues identified related to the change. One is INSERT_SUBREG cannot guarantee source and dest to be the same register. It mostly happens on O0. The other one is zero_extend is not a chain node, as a result, we will lose the chain for SETZUCCr. Full diff: https://github.com/llvm/llvm-project/pull/172192.diff 2 Files Affected:
diff --git a/llvm/lib/Target/X86/X86InstrCMovSetCC.td b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
index b1599f2f37045..0b9172c1f2b6e 100644
--- a/llvm/lib/Target/X86/X86InstrCMovSetCC.td
+++ b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
@@ -167,10 +167,6 @@ let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1,
}
}
-let Predicates = [HasZU] in
- def : Pat<(i32 (zext (X86setcc timm:$cond, EFLAGS))),
- (INSERT_SUBREG (i32 (IMPLICIT_DEF)), (SETZUCCr ccode:$cond), sub_8bit)>;
-
// SALC is an undocumented instruction. Information for this instruction can be found
// here http://www.rcollins.org/secrets/opcodes/SALC.html
// Set AL if carry.
diff --git a/llvm/test/CodeGen/X86/apx/setzucc.ll b/llvm/test/CodeGen/X86/apx/setzucc.ll
index d32ccf877137e..6eb2d6966ecd8 100644
--- a/llvm/test/CodeGen/X86/apx/setzucc.ll
+++ b/llvm/test/CodeGen/X86/apx/setzucc.ll
@@ -89,15 +89,3 @@ bb1:
bb2:
ret i32 0
}
-
-define i32 @highmask_i32_mask32(i32 %val) {
-; CHECK-LABEL: highmask_i32_mask32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: testl $-1048576, %edi # imm = 0xFFF00000
-; CHECK-NEXT: setzune %al
-; CHECK-NEXT: retq
- %and = and i32 %val, -1048576
- %cmp = icmp ne i32 %and, 0
- %ret = zext i1 %cmp to i32
- ret i32 %ret
-}
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/39/builds/9107 Here is the relevant piece of the build log for the reference |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/110/builds/6793 Here is the relevant piece of the build log for the reference |
This reverts commit 2612dc9 but keeps
Predicates = [HasNDD]removed.There are two issues identified related to the change. One is INSERT_SUBREG cannot guarantee source and dest to be the same register. It mostly happens on O0. The other one is zero_extend is not a chain node, as a result, we will lose the chain for SETZUCCr.