OpenTitan patches on 10.2.0 #322
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These changes are specific to our fork and are either being dropped by open pull requests or will not be needed upstream. Co-authored-by: Emmanuel Blot <eblot@rivosinc.com> Co-authored-by: Loïc Lefort <loic@rivosinc.com> Signed-off-by: James Wainwright <james.wainwright@lowrisc.org>
The option is disabled by default. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Demangler code taken from GNU libiberty. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
This changes enables providing custom address translation engine. OpenTitan does not have an MMU, but support a custom virtual remapper. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: James Wainwright <james.wainwright@lowrisc.org>
Add the capability to maintain CPU in reset. The Resettable API has added a new way to manage reset, where resetting a device not only trigger a transient reset, but enable devices to be held in reset and manage a reset tree. This commit adds this resettable feature to CPUs, so they can be held in reset and released once other devices in the machine are released. The CPU reset is no longer a transient state but a stable state. The CPU reset state can be tracked with a new attribute: held_in_reset. This feature is useful to better emulate SoC like OpenTitan where the CPU is actively held in Reset while other devices complete their own initialization, such as the power manager and ROM controller. It also enables to update the CPU configuration and attributes while the CPUs are held in reset. On RISC-V CPUs, reset vector and mtvec registers for example can be updated before releasing the harts from reset. Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: James Wainwright <james.wainwright@lowrisc.org>
Signed-off-by: James Wainwright <james.wainwright@lowrisc.org>
This machine emulates the Ibex Demo System [0] and includes GPIO, SPI device, a timer, UART, and a debug module. There is an st7735 LCD display connected to the SPI device. [0]: https://github.com/lowRISC/ibex-demo-system
The emulator is written in Rust and based on Greg Chadwick's RRS RISC-V simulator. Signed-off-by: James Wainwright <james.wainwright@lowrisc.org>
Signed-off-by: James Wainwright <james.wainwright@lowrisc.org>
Signed-off-by: James Wainwright <james.wainwright@lowrisc.org>
These machines come with many new blocks, scripts, and documentation. Co-authored-by: Loïc Lefort <loic@rivosinc.com> Signed-off-by: James Wainwright <james.wainwright@lowrisc.org>
These scripts are needed for generating the OTP and flash images and can be used to interact with IO peripherals and generate data. Signed-off-by: James Wainwright <james.wainwright@lowrisc.org>
Includes GitLab flows, though these are not tested in the open source repository.
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These commits are squashed versions of all the changes in our fork on top of upstream 10.2.0. The final repository matches our fork exactly (at time of writing).
I've tested that each commit compiles but haven't run the machines on every commit.
The commits are split to make them easier to rebase and resolve conflicts. Almost all OpenTitan changes are in a single commit because they introduce new files and will not conflict with anything already in the repository.