CORDIC (Vectoring mode) — Verilog

A compact, parameterized CORDIC top module for computing atan2(y, x) (vectoring mode) with fixed‑point arithmetic.

The design is organized as a pipeline of stages (one per iteration). Angles are looked up from a packed LUT of atan(2^-i) values.

---

Interface

module cordic_top_module #(
    parameter WORD_LENGTH = 16,
    parameter N_ITERATION = 6          // use 1..10 with the provided LUT
)(
    input  wire signed [WORD_LENGTH-1:0] x_in,
    input  wire signed [WORD_LENGTH-1:0] y_in,
    input  wire signed [WORD_LENGTH-1:0] z_in,   // initial angle (usually 0)
    output wire signed [WORD_LENGTH-1:0] x_out,  // magnitude projection
    output wire signed [WORD_LENGTH-1:0] y_out,  // driven toward 0 in vectoring
    output wire signed [WORD_LENGTH-1:0] z_out,  // accumulated angle
    input  wire clk,
    input  wire rst
);

• Angles (z, LUT) are Q8.8 in degrees: e.g., 45° = 45 * 2^8 = 11520 (16'h2D00).
• x/y use the same signed WORD_LENGTH format consistently across the pipeline (you can treat them as Qm.n; the design does not reinterpret their scale).
• N_ITERATION selects how many pipeline stages are instantiated (error ↓ as iterations ↑). The LUT is provided up to 10 iterations.

---

Packed LUT

ATAN_LUT_PACKED stores atan(2^-i) for i=0..9 in degrees(Q8.8), MSB-first. Each stage extracts its slice with compile‑time indices, so no run‑time indexing is needed.

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Results

The plot compares the module's z_out (blue, degrees) against MATLAB atan2 (orange, dashed) over a sweep of input vectors. The curves overlap almost perfectly across the whole range (≈ −80° to +80° here). The tiny residual gap at the extremes is expected from:

• finite iterations (N_ITERATION = 6 by default),
• fixed‑point quantization (16‑bit, Q8.8 for angles),
• LUT rounding.

If you need lower error, increase N_ITERATION (up to 10 with the current LUT) or widen WORD_LENGTH.

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How to simulate (Vivado xsim)

# From the project root (adjust paths to your files)
xvlog sources_1/new/cordic_stage.v cordic_top_module.v sim_1/new/cordic_top_module_tb.v
xelab cordic_top_module_tb -s cordic_tb
xsim cordic_tb --runall

Your testbench should drive (x_in, y_in) sweeps and capture z_out for comparison with a reference (atan2) in your favorite tool.

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Notes

• The CORDIC gain is not compensated in this top module (typical for vectoring/atan use); for rotation mode use, apply the inverse gain externally if you require unity gain on (x,y).
• rst is synchronous in the provided stage template (adjust to your style if you need async).
• This top is agnostic to sign conventions; just be consistent across your system.