Dev/generic arch

src/main/scala/caravan/bus/common/Transaction.scala

@@ -1,5 +1,7 @@
 package caravan.bus.common
 import chisel3._
+import chisel3.util.DecoupledIO
+
 
 /**
  * This abstract class provides a template for other protocols to implement the transaction wires.
@@ -27,8 +29,51 @@ class BusDevice extends Bundle
 
 /** The HostAdapter and DeviceAdapter is a class from which each host/device adapter
  * of a specific bus protocol will extend (beneficial for switch) */
-abstract class DeviceAdapter extends Module
-abstract class HostAdapter extends Module
+abstract class DeviceAdapterIO extends Bundle
+{
+  val reqOut: DecoupledIO[AbstrRequest]
+  val rspIn : DecoupledIO[AbstrResponse]
+  val slaveTransmitter: DecoupledIO[BusDevice]
+  val masterReceiver: DecoupledIO[BusHost]
+}
+abstract class DeviceAdapter extends Module{
+  val io: DeviceAdapterIO
+}
+
+abstract class HostAdapterIO extends Bundle
+{
+  val reqIn: DecoupledIO[AbstrRequest]
+  val rspOut: DecoupledIO[AbstrResponse]
+  val masterTransmitter: DecoupledIO[BusHost]
+  val slaveReceiver: DecoupledIO[BusDevice]
+}
+
+abstract class HostAdapter extends Module {
+  val io: HostAdapterIO
+
+  def getAddressPin: UInt
+}
+
+abstract class ErrorDeviceIO extends Bundle
+{
+  val slaveTransmitter: DecoupledIO[BusDevice]
+  val masterReceiver: DecoupledIO[BusHost]
+}
+abstract class ErrorDevice extends Module{
+  val io: ErrorDeviceIO
+}
+
+abstract class BusAdapterIO extends Bundle
+{
+  val reqIn: DecoupledIO[AbstrRequest]
+  val rspOut: DecoupledIO[AbstrResponse]
+  val reqOut: DecoupledIO[AbstrRequest]
+  val rspIn: DecoupledIO[AbstrResponse]
+}
+abstract class BusAdapter extends Module
+{
+  val io: BusAdapterIO
+}
 
 // created a trait so that each specific bus protocol
 // can extend from it (beneficial for type paremterization)

src/main/scala/caravan/bus/tilelink/Harness.scala

@@ -35,8 +35,8 @@ class TilelinkHarness/*(programFile: Option[String])*/(implicit val config: Tile
 
   tlHost.io.rspOut.ready := true.B  // IP always ready to accept data from wb host
 
-  tlHost.io.tlMasterTransmitter <> tlSlave.io.tlMasterReceiver
-  tlSlave.io.tlSlaveTransmitter <> tlHost.io.tlSlaveReceiver
+  tlHost.io.masterTransmitter <> tlSlave.io.masterReceiver
+  tlSlave.io.slaveTransmitter <> tlHost.io.slaveReceiver
 
   //tlHost.io.reqIn.valid := Mux(tlHost.io.reqIn.ready, io.valid, false.B)
   tlHost.io.reqIn.valid := io.valid

src/main/scala/caravan/bus/tilelink/SwitchHarness.scala

@@ -49,18 +49,18 @@ class SwitchHarness/*(programFile: Option[String])*/(implicit val config: Tileli
   host.io.reqIn.bits.activeByteLane := io.byteLane
   host.io.reqIn.bits.isWrite := io.isWrite
 
-  switch.io.hostIn <> host.io.tlMasterTransmitter
-  switch.io.hostOut <> host.io.tlSlaveReceiver
+  switch.io.hostIn <> host.io.masterTransmitter
+  switch.io.hostOut <> host.io.slaveReceiver
 
   for (i <- 0 until devices.size) {
-    switch.io.devIn(devices(i)._2.litValue().toInt) <> devices(i)._1.asInstanceOf[TilelinkDevice].io.tlSlaveTransmitter
-    switch.io.devOut(devices(i)._2.litValue().toInt) <> devices(i)._1.asInstanceOf[TilelinkDevice].io.tlMasterReceiver
+    switch.io.devIn(devices(i)._2.litValue().toInt) <> devices(i)._1.asInstanceOf[TilelinkDevice].io.slaveTransmitter
+    switch.io.devOut(devices(i)._2.litValue().toInt) <> devices(i)._1.asInstanceOf[TilelinkDevice].io.masterReceiver
   }
 
-  switch.io.devOut(devices.size) <> tlErr.io.tlMasterReceiver
-  switch.io.devIn(devices.size) <> tlErr.io.tlSlaveTransmitter
+  switch.io.devOut(devices.size) <> tlErr.io.masterReceiver
+  switch.io.devIn(devices.size) <> tlErr.io.slaveTransmitter
 
-  switch.io.devSel := BusDecoder.decode(host.io.tlMasterTransmitter.bits.a_address, addressMap)
+  switch.io.devSel := BusDecoder.decode(host.io.masterTransmitter.bits.a_address, addressMap)
   dccmDev.io.reqOut <> memCtrl.io.req
   dccmDev.io.rspIn <> memCtrl.io.rsp
 

src/main/scala/caravan/bus/tilelink/TilelinkAdapter.scala

@@ -3,26 +3,31 @@ package caravan.bus.tilelink
 import chisel3._ 
 import chisel3.util._
 
-class TilelinkAdapter(implicit val config:TilelinkConfig) extends Module {
-    val io = IO(new Bundle{
+import caravan.bus.common._
 
-        /*  MASTER SIDE  */
-        val reqIn =  Flipped(Decoupled(new TLRequest))
-        val rspOut = Decoupled(new TLResponse)
+class TilelinkAdapterIO(implicit val config:TilelinkConfig) extends BusAdapterIO{
 
-        /*  SLAVE SIDE */
-        val reqOut = Decoupled(new TLRequest)
-        val rspIn = Flipped(Decoupled(new TLResponse))
-    })
+    /*  MASTER SIDE  */
+    val reqIn =  Flipped(Decoupled(new TLRequest))
+    val rspOut = Decoupled(new TLResponse)
+
+    /*  SLAVE SIDE */
+    val reqOut = Decoupled(new TLRequest)
+    val rspIn = Flipped(Decoupled(new TLResponse))
+
+}
+
+class TilelinkAdapter(implicit val config:TilelinkConfig) extends BusAdapter {
+    val io = IO(new TilelinkAdapterIO)
 
     val tlHost = Module(new TilelinkHost)
     val tlSlave = Module(new TilelinkDevice)
 
     /*  Connecting Master Interconnects  */
-    tlHost.io.tlMasterTransmitter <> tlSlave.io.tlMasterReceiver
+    tlHost.io.masterTransmitter <> tlSlave.io.masterReceiver
 
     /*  Connecting Slave Interconnects  */
-    tlSlave.io.tlSlaveTransmitter <> tlHost.io.tlSlaveReceiver
+    tlSlave.io.slaveTransmitter <> tlHost.io.slaveReceiver
 
     /*  Sending Request in Master  */
     tlHost.io.reqIn <> io.reqIn