Timer, Programmable UART and SRAM1kb is added.

src/main/resources/sram/sram.v

@@ -0,0 +1,144 @@
+// SPDX-FileCopyrightText: 2020 fabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+//`default_nettype none
+// OpenRAM SRAM model
+// Words: 256
+// Word size: 32
+// Write size: 8
+
+module sram #(
+  parameter NUM_WMASKS = 4,
+  parameter DATA_WIDTH = 32,
+  parameter ADDR_WIDTH = 10,
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH,
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 3,
+  parameter IZERO   = 0 , // binary / Initial RAM with zeros (has priority over INITFILE)
+  parameter IFILE   = "" 
+)
+(
+/*`ifdef USE_POWER_PINS
+	vdd,
+	gnd,
+`endif */
+// Port 0: RW
+    clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+    clk1,csb1,addr1,dout1
+  );
+
+
+/*`ifdef USE_POWER_PINS
+  inout vdd;
+  inout gnd;
+`endif
+  */
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [NUM_WMASKS-1:0]   wmask0; // write mask
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+  input  clk1; // clock
+  input   csb1; // active low chip select
+  input [ADDR_WIDTH-1:0]  addr1;
+  output [DATA_WIDTH-1:0] dout1;
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [NUM_WMASKS-1:0]   wmask0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    wmask0_reg = wmask0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+    //dout0 = 32'bx0;
+/*`ifdef DBG
+    if ( !csb0_reg && web0_reg ) 
+      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    if ( !csb0_reg && !web0_reg )
+      $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+`endif 
+*/   end
+
+  reg  csb1_reg;
+  reg [ADDR_WIDTH-1:0]  addr1_reg;
+  reg [DATA_WIDTH-1:0]  dout1;
+
+  // All inputs are registers
+  always @(posedge clk1)
+  begin
+    csb1_reg = csb1;
+    addr1_reg = addr1;
+//`ifdef DBG
+//    if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+//         $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+//    dout1 = 32'bx;
+//    if ( !csb1_reg ) 
+//      $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+//`endif  
+   end
+integer i;
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+initial
+    if (IZERO)
+      for (i=0; i<RAM_DEPTH; i=i+1) mem[i] = {DATA_WIDTH{1'b0}};
+    else
+      if (IFILE != "") $readmemh(IFILE, mem);
+
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg ) begin
+        if (wmask0_reg[0])
+                mem[addr0_reg][7:0] = din0_reg[7:0];
+        if (wmask0_reg[1])
+                mem[addr0_reg][15:8] = din0_reg[15:8];
+        if (wmask0_reg[2])
+                mem[addr0_reg][23:16] = din0_reg[23:16];
+        if (wmask0_reg[3])
+                mem[addr0_reg][31:24] = din0_reg[31:24];
+    end
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+  // Memory Read Block Port 1
+  // Read Operation : When web1 = 1, csb1 = 0/ 
+ always @ (negedge clk1)
+  begin : MEM_READ1
+   if (!csb1_reg)
+       dout1 <= #(DELAY) mem[addr1_reg];
+  end
+
+endmodule
+//`default_nettype wire
+

src/main/scala/jigsaw/SpiFlashHarness.scala

@@ -0,0 +1,90 @@
+package jigsaw
+import caravan.bus.tilelink.{TLRequest, TLResponse, TilelinkConfig, TilelinkDevice, TilelinkHost}
+import caravan.bus.wishbone.{WBRequest, WBResponse, WishboneConfig, WishboneDevice, WishboneHost}
+import chisel3._
+import chisel3.stage.ChiselStage
+import chisel3.util.Decoupled
+import jigsaw.peripherals.spiflash.{Config,SpiFlash}
+
+class SpiFlashHarness(implicit val config: WishboneConfig) extends Module {
+  val io = IO(new Bundle {
+
+    // bus interconnect interfaces
+    val req = Flipped(Decoupled(new WBRequest()))
+    val rsp = Decoupled(new WBResponse())
+
+    // master spi interfaces
+    val cs_n = Output(Bool())
+    val sclk = Output(Bool())
+    val mosi = Output(Bool())
+    val miso = Input(Bool())
+
+  })
+  val hostAdapter = Module(new WishboneHost())
+  val deviceAdapter = Module(new WishboneDevice())
+  val spi = Module(new SpiFlash(new WBRequest(), new WBResponse()))
+
+  hostAdapter.io.reqIn <> io.req
+  io.rsp <> hostAdapter.io.rspOut
+  hostAdapter.io.wbMasterTransmitter <> deviceAdapter.io.wbMasterReceiver
+  hostAdapter.io.wbSlaveReceiver <> deviceAdapter.io.wbSlaveTransmitter
+
+  spi.io.req <> deviceAdapter.io.reqOut
+  spi.io.rsp <> deviceAdapter.io.rspIn
+
+
+    io.cs_n := spi.io.cs_n
+    io.sclk := spi.io.sclk
+    io.mosi := spi.io.mosi
+
+    spi.io.miso := io.miso
+}
+
+object SpiFlashDriverWB extends App {
+  implicit val config = WishboneConfig(32,32)
+  // implicit val spiConfig = Config()
+  (new ChiselStage).emitVerilog(new SpiFlashHarness())
+}
+
+
+
+
+class SpiFlashHarnessTL(implicit val config: TilelinkConfig) extends Module {
+  val io = IO(new Bundle {
+
+    // bus interconnect interfaces
+    val req = Flipped(Decoupled(new TLRequest()))
+    val rsp = Decoupled(new TLResponse())
+
+    // master spi interfaces
+    val cs_n = Output(Bool())
+    val sclk = Output(Bool())
+    val mosi = Output(Bool())
+    val miso = Input(Bool())
+
+  })
+  val hostAdapter = Module(new TilelinkHost())
+  val deviceAdapter = Module(new TilelinkDevice())
+  val spi = Module(new SpiFlash(new TLRequest(), new TLResponse()))
+
+  hostAdapter.io.reqIn <> io.req
+  io.rsp <> hostAdapter.io.rspOut
+  hostAdapter.io.tlMasterTransmitter <> deviceAdapter.io.tlMasterReceiver
+  hostAdapter.io.tlSlaveReceiver <> deviceAdapter.io.tlSlaveTransmitter
+
+  spi.io.req <> deviceAdapter.io.reqOut
+  spi.io.rsp <> deviceAdapter.io.rspIn
+
+
+    io.cs_n := spi.io.cs_n
+    io.sclk := spi.io.sclk
+    io.mosi := spi.io.mosi
+
+    spi.io.miso := io.miso
+}
+
+object SpiFlashDriverTL extends App {
+  implicit val config = TilelinkConfig()
+  // implicit val spiConfig = Config()
+  (new ChiselStage).emitVerilog(new SpiFlashHarnessTL())
+}

src/main/scala/jigsaw/SpiHarness.scala

@@ -4,9 +4,9 @@ import caravan.bus.wishbone.{WBRequest, WBResponse, WishboneConfig, WishboneDevi
 import chisel3._
 import chisel3.stage.ChiselStage
 import chisel3.util.Decoupled
-import jigsaw.peripherals.spiflash.{Config,Spi}
+import jigsaw.peripherals.spi.{Config,Spi}
 
-class SpiHarness(implicit val config: WishboneConfig, spiConfig:Config) extends Module {
+class SpiHarness(implicit val config: WishboneConfig) extends Module {
   val io = IO(new Bundle {
 
     // bus interconnect interfaces
@@ -42,14 +42,14 @@ class SpiHarness(implicit val config: WishboneConfig, spiConfig:Config) extends
 
 object SpiDriverWB extends App {
   implicit val config = WishboneConfig(32,32)
-  implicit val spiConfig = Config()
+  // implicit val spiConfig = Config()
   (new ChiselStage).emitVerilog(new SpiHarness())
 }
 
 
 
 
-class SpiHarnessTL(implicit val config: TilelinkConfig, spiConfig:Config) extends Module {
+class SpiHarnessTL(implicit val config: TilelinkConfig) extends Module {
   val io = IO(new Bundle {
 
     // bus interconnect interfaces
@@ -85,6 +85,6 @@ class SpiHarnessTL(implicit val config: TilelinkConfig, spiConfig:Config) extend
 
 object SpiDriverTL extends App {
   implicit val config = TilelinkConfig()
-  implicit val spiConfig = Config()
+  // implicit val spiConfig = Config()
   (new ChiselStage).emitVerilog(new SpiHarnessTL())
 }

src/main/scala/jigsaw/SramHarness.scala

@@ -0,0 +1,65 @@
+package jigsaw
+import caravan.bus.tilelink.{TLRequest, TLResponse, TilelinkConfig, TilelinkDevice, TilelinkHost}
+import caravan.bus.wishbone.{WBRequest, WBResponse, WishboneConfig, WishboneDevice, WishboneHost}
+import chisel3._
+import chisel3.stage.ChiselStage
+import chisel3.util.Decoupled
+// import jigsaw.peripherals.spiflash.{Config,Spi}
+import jigsaw.rams.sram._
+
+class SramHarness(programFile:Option[String], val AW:Int = 10)(implicit val config: WishboneConfig) extends Module {
+  val io = IO(new Bundle {
+
+    // bus interconnect interfaces
+    val req = Flipped(Decoupled(new WBRequest()))
+    val rsp = Decoupled(new WBResponse())
+  })
+  val hostAdapter = Module(new WishboneHost())
+  val deviceAdapter = Module(new WishboneDevice())
+  val sram = Module(new SRAM1kb(new WBRequest(), new WBResponse())(programFile, AW))
+
+  hostAdapter.io.reqIn <> io.req
+  io.rsp <> hostAdapter.io.rspOut
+  hostAdapter.io.wbMasterTransmitter <> deviceAdapter.io.wbMasterReceiver
+  hostAdapter.io.wbSlaveReceiver <> deviceAdapter.io.wbSlaveTransmitter
+
+  sram.io.req <> deviceAdapter.io.reqOut
+  sram.io.rsp <> deviceAdapter.io.rspIn
+}
+
+object SramDriverWB extends App {
+  implicit val config = WishboneConfig(32,32)
+//   implicit val spiConfig = Config()
+  (new ChiselStage).emitVerilog(new SramHarness(None))
+}
+
+
+
+
+class SramHarnessTL(programFile:Option[String], val AW:Int = 10)(implicit val config: TilelinkConfig ) extends Module {
+  val io = IO(new Bundle {
+
+    // bus interconnect interfaces
+    val req = Flipped(Decoupled(new TLRequest()))
+    val rsp = Decoupled(new TLResponse())
+
+  })
+  val hostAdapter = Module(new TilelinkHost())
+  val deviceAdapter = Module(new TilelinkDevice())
+  val sram = Module(new SRAM1kb(new TLRequest(), new TLResponse())(programFile, AW))
+
+  hostAdapter.io.reqIn <> io.req
+  io.rsp <> hostAdapter.io.rspOut
+  hostAdapter.io.tlMasterTransmitter <> deviceAdapter.io.tlMasterReceiver
+  hostAdapter.io.tlSlaveReceiver <> deviceAdapter.io.tlSlaveTransmitter
+
+  sram.io.req <> deviceAdapter.io.reqOut
+  sram.io.rsp <> deviceAdapter.io.rspIn
+
+}
+
+object SramDriverTL extends App {
+  implicit val config = TilelinkConfig()
+//   implicit val spiConfig = Config()
+  (new ChiselStage).emitVerilog(new SramHarnessTL(None))
+}