Compressed (C) Extension Fix

.readthedocs.yaml

@@ -0,0 +1,13 @@
+version: 2
+
+build:
+  os: ubuntu-22.04
+  tools:
+    python: "3.10"
+
+sphinx:
+  configuration: docs/conf.py
+
+python:
+  install:
+    - requirements: docs/requirements.txt

README.md

@@ -1,53 +1,258 @@
-# NucleusRV
+# 🚀 NucleusRV
 
-[![Join the chat at https://gitter.im/merledu/nucleusrv](https://badges.gitter.im/merledu/nucleusrv.svg)](https://gitter.im/merledu/nucleusrv?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
+<p align="center">
+  <b>A 5-Stage Pipelined RV32I CPU written in Chisel</b><br>
+  Lightweight • Educational • Hackable
+</p>
 
-A chisel based riscv 5-stage pipelined cpu design, implementing 32-bit version of the ISA (incomplete).
+<p align="center">
+  <a href="https://github.com/merledu/nucleusrv/stargazers">
+    <img src="https://img.shields.io/github/stars/merledu/nucleusrv?style=for-the-badge" />
+  </a>
+  <a href="https://github.com/merledu/nucleusrv/network/members">
+    <img src="https://img.shields.io/github/forks/merledu/nucleusrv?style=for-the-badge" />
+  </a>
+  <a href="https://github.com/merledu/nucleusrv/issues">
+    <img src="https://img.shields.io/github/issues/merledu/nucleusrv?style=for-the-badge" />
+  </a>
+  <a href="https://gitter.im/merledu/nucleusrv">
+    <img src="https://img.shields.io/badge/chat-gitter-brightgreen?style=for-the-badge" />
+  </a>
+</p>
 
+---
 
-## Dependencies
+## 📌 Overview
 
-* [`verilator >= v5.002`](https://verilator.org/guide/latest/install.html): Simulation
-* [`riscv-gnu-toolchain`](https://github.com/riscv/riscv-gnu-toolchain): To build the C program
+**NucleusRV** is a Chisel-based implementation of a **5-stage pipelined RISC-V processor** supporting the 32-bit base ISA.
 
+It is designed for:
 
-## Getting Started
+* 🎓 Learning computer architecture
+* 🧪 Experimenting with RISC-V microarchitecture
+* 🛠 Extending ISA features
+* 🔬 Academic research & hobby development
 
-### Clone
+> Current ISA Support: **RV32IMAFC-Zicsr**
 
-```sh
+---
+
+## 🧠 Architecture
+
+* 5-Stage Pipeline
+
+  * IF — Instruction Fetch
+  * ID — Instruction Decode
+  * EX — Execute
+  * MEM — Memory
+  * WB — Writeback
+* Written in **Chisel**
+* Simulated using **Verilator**
+* Supports architectural test execution via **RISCOF**
+
+---
+
+## 🛠 Dependencies
+
+| Tool                                                                    | Purpose                 |
+| ----------------------------------------------------------------------- | ----------------------- |
+| [`verilator >= 5.002`](https://verilator.org/guide/latest/install.html) | Simulation              |
+| [`riscv-gnu-toolchain`](https://github.com/riscv/riscv-gnu-toolchain)   | Building C programs     |
+| `sbt`                                                                   | Scala/Chisel build tool |
+| `Java 17`                                                               | Required runtime        |
+
+---
+
+## 📥 Getting Started
+
+### 1️⃣ Clone the Repository
+
+```bash
 git clone --recurse-submodules https://github.com/merledu/nucleusrv.git
+cd nucleusrv
 ```
 
-### Running RISC-V assembly
+---
+
+## ▶ Running RISC-V Assembly
+
+### Generate Verilog
 
-```sh
-sbt "nucleusrv.components.NRVDriver --imem /path/to/imem/hex/file --dmem /path/to/dmem/hex/file --target-dir /path/to/output/dir"
+```bash
+sbt "nucleusrv.components.NRVDriver \
+--imem /path/to/imem.hex \
+--dmem /path/to/dmem.hex \
+--target-dir /path/to/output"
+```
+
+### Build & Run with Verilator
+
+```bash
 export NRV_ROOT=$PWD
-cd /path/to/output/dir
-verilator --cc --exe --build --trace --no-timing $NRV_ROOT/tb_Top.cpp Top.v
+cd /path/to/output
+
+verilator --cc --exe --build --trace --no-timing \
+$NRV_ROOT/tb_Top.cpp Top.v
+
 ./obj_dir/VTop
 ```
 
-Waveform will can be found at `/path/to/output/dir/logs`.
+📊 Waveforms will be available at:
+
+```
+/path/to/output/logs
+```
+
+---
+
+## 🧪 Running RISC-V Architectural Tests
+
+Make sure `verilator` and `riscv-gnu-toolchain` are in your `PATH`.
 
-### Running RISC-V Architectural Tests
-* Make sure to have the RISC-V GNU Toolchain and Verilator in your `PATH`.
-* Create a python virtual environment and setup `riscv-arch-test`.
-```sh
+### Setup Python Environment
+
+```bash
 python3 -m venv .venv
 source .venv/bin/activate
-pip3 install -e riscof/riscv-arch-test/riscv-ctg riscof/riscv-arch-test/riscv-isac
-pip3 install git+https://github.com/riscv/riscof.git
+
+pip install -e riscof/riscv-arch-test/riscv-ctg \
+               riscof/riscv-arch-test/riscv-isac
+
+pip install git+https://github.com/riscv/riscof.git
 ```
-* Run `run_riscv_arch_tests.py` in root directory.
-```sh
+
+### Run Tests
+
+```bash
 python3 run_riscv_arch_tests.py
 ```
 
-### Building C Programs
-* In `tools/tests` directory, create a folder and write c program in the `main.c` file
-* Run `make PROGRAM=<your_newly_created_test_folder_name`> inside tools directory
-* Build the program with `sbt` command listed above. Make sure you are in root directory
+---
+
+## 🧾 Building C Programs
+
+1. Navigate to:
+
+```
+tools/tests
+```
+
+2. Create a new folder and add your `main.c`
+
+3. Build:
+
+```bash
+cd tools
+make PROGRAM=<your_test_folder_name>
+```
+
+4. Generate Verilog using `sbt` as shown earlier.
+
+---
+
+### 🔹 Optional: Direct HEX Execution
+
+Instead of compiling C:
+
+* Write hex instructions directly into:
+
+```
+tools/out/program.hex
+```
+
+---
+
+# ⚠️ Troubleshooting
+
+## 🔥 If `sbt` Breaks
+
+Sometimes `sbt` cache becomes corrupted.
+
+If you see unexplained build errors:
+
+```bash
+rm -rf project/ target/
+sbt clean
+sbt compile
+```
+
+If issues persist:
+
+```bash
+rm -rf ~/.ivy2/cache
+rm -rf ~/.sbt
+```
+
+Then retry.
+
+---
+
+# ✅ Tested Environment (Last Known Working Setup)
+
+If builds fail, verify your versions match below.
+
+## 🛠 SBT
+
+```
+Project SBT Version: 1.12.0
+Runner SBT Version:  1.12.0
+```
+
+---
+
+## ☕ Java
+
+```
+OpenJDK 17.0.18
+```
+
+⚠️ **Java 25 does NOT work. Use Java 17.**
+
+---
+
+## 🐧 Arch Linux Users
+
+Arch defaults to newer Java versions.
+You must switch to Java 17:
+
+```bash
+sudo pacman -S jdk17-openjdk
+sudo archlinux-java set java-17-openjdk
+java -version
+```
+
+Ensure it prints:
+
+```
+openjdk version "17.x.x"
+```
+
+---
+
+# 🤝 Contributing
+
+Contributions are welcome!
+
+1. Fork the repo
+2. Create a feature branch
+3. Submit a PR
+
+For major changes, please open an issue first.
+
+---
+
+# 💬 Community
+
+Join the discussion:
+
+👉 [https://gitter.im/merledu/nucleusrv](https://gitter.im/merledu/nucleusrv)
+
+---
+
+# ⭐ Support
+
+If this project helped you:
 
-* Optionally, you can skip writing/building c program and directly write hex instructions to `program.hex` file in `tools/out` directory.
+* Star the repo
+* Share it
+* Build something cool with it

docs/requirements.txt

@@ -0,0 +1,2 @@
+sphinx
+sphinx-rtd-theme

riscof/nucleusrv/nucleusrv_isa.yaml

@@ -1,6 +1,6 @@
 hart_ids: [0]
 hart0:
-  ISA: RV32IMFZicsr
+  ISA: RV32IMFCZicsr
   physical_addr_sz: 32
   User_Spec_Version: '2.3'
   supported_xlen: [32]

riscof/spike/riscof_spike.py

@@ -74,12 +74,12 @@ def build(self, isa_yaml, platform_yaml):
             self.isa += 'm'
         if "A" in ispec["ISA"]:
             self.isa += 'a'
-        if "C" in ispec["ISA"]:
-            self.isa += 'c'
         if "F" in ispec["ISA"]:
             self.isa += 'f'
         if "D" in ispec["ISA"]:
             self.isa += 'd'
+        if "C" in ispec["ISA"]:
+            self.isa += 'c'
 
         # based on the validated isa and platform configure your simulator or
         # build your RTL here

src/main/scala/components/CompressedDecoder.scala

@@ -287,4 +287,10 @@ class CompressedDecoder extends Module {
       io.is_comp := false.B
       io.instruction_o := io.instruction_i
   }
+
+  when(io.instruction_i === "h00000013".asUInt(32.W)){
+    // nop -- pass down -- not is_comp
+    io.is_comp := false.B
+    io.instruction_o := io.instruction_i
+  }
 }

src/main/scala/components/Configs.scala

@@ -4,7 +4,7 @@ case class Configs(
     XLEN    : Int     = 32,
     M       : Boolean = true,
     F       : Boolean = true,
-    C       : Boolean = false,
+    C       : Boolean = true,
     A       : Boolean = true,
     Zicsr   : Boolean = true,
     TRACE   : Boolean = true,