GitHub - mnmhdanas/Parallel-IN-Serial-OUT: In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to 1. For every positive edge triggering of clock signal, the data shifts from one stage to the next. So, we will get the serial output from the right most D flip-flop.

Name		Name	Last commit message	Last commit date
piso.v		piso.v
piso_waveform.jpg		piso_waveform.jpg
pisotb.v		pisotb.v

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In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to 1. For every positive edge triggering of clock signal, the data shifts from one stage to the next. So, we will get the serial output from the right most D flip-flop.

digital-electronics piso shift-register verilog

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