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tmatmul and tgemv Besides low precision#462

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yuqiha wants to merge 4 commits into
mouliangyu:feature-vpto-backendfrom
yuqiha:matmul_1
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tmatmul and tgemv Besides low precision#462
yuqiha wants to merge 4 commits into
mouliangyu:feature-vpto-backendfrom
yuqiha:matmul_1

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@yuqiha

@yuqiha yuqiha commented May 29, 2026

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Comment thread lib/TileOps/tmatmul_template.py Outdated

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这里似乎写反了,n应该取valid_col

Comment thread lib/TileOps/tmatmul_acc_template.py Outdated
)
def template_tmatmul_acc(acc_in: pto.Tile, lhs: pto.Tile, rhs: pto.Tile, dst: pto.Tile):
m, k = lhs.valid_shape
n, _ = rhs.valid_shape

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这里n取成valid_row了,应该是valid_col

Comment thread lib/TileOps/tgemv_template.py Outdated
)
def template_tgemv(lhs: pto.Tile, rhs: pto.Tile, acc: pto.Tile):
_, k = lhs.valid_shape
n, _ = rhs.valid_shape

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这里也反了

Comment thread lib/TileOps/tgemv_acc_template.py Outdated
)
def template_tgemv_acc(acc_in: pto.Tile, lhs: pto.Tile, rhs: pto.Tile, dst: pto.Tile):
_, k = lhs.valid_shape
n, _ = rhs.valid_shape

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这里也反了

Comment thread lib/TileOps/tmatmul_bias_template.py Outdated
(pto.f16, pto.f16, pto.f16, pto.f32),
(pto.f16, pto.f16, pto.bf16, pto.f32),
(pto.f16, pto.f16, pto.f32, pto.f32),
(pto.bf16, pto.bf16, pto.bf16, pto.f32),

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TMatmul要求bias.dtype == dst.dtype,这几个dtypes类型有问题


pto.set_flag["PIPE_MTE1", "PIPE_M", "EVENT_ID0"]
pto.wait_flag["PIPE_MTE1", "PIPE_M", "EVENT_ID0"]
pto.mad %l0a, %l0b, %l0c, %c48_i64, %c64_i64, %c64_i64 disable_gemv

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无效测例,没有走TileOp ---ExpandTileOp---> VectorOp的路径


pto.set_flag["PIPE_MTE1", "PIPE_M", "EVENT_ID0"]
pto.wait_flag["PIPE_MTE1", "PIPE_M", "EVENT_ID0"]
pto.mad %l0a, %l0b, %l0c, %c16_i64, %c64_i64, %c320_i64

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无效测例


pto.set_flag["PIPE_MTE1", "PIPE_M", "EVENT_ID1"]
pto.wait_flag["PIPE_MTE1", "PIPE_M", "EVENT_ID1"]
pto.mad_acc %l0a, %l0b, %l0c, %c16_i64, %c16_i64, %c16_i64 disable_gemv

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无效测例


pto.set_flag["PIPE_MTE1", "PIPE_M", "EVENT_ID0"]
pto.wait_flag["PIPE_MTE1", "PIPE_M", "EVENT_ID0"]
pto.mad_bias %l0a, %l0b, %l0c, %bias_ptr, %c16_i64, %c16_i64, %c16_i64 disable_gemv

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无效测例

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2 participants