Detailed VMI vs MI design comparison, using Quant&RoPE demo walk-through

[learning-chip]

Some algorithm background:

• The block_mx_quant SIMD VF implementation closely mirrors CANN/AscendC dynamic_block_mx_quant. It's similar to open-source TileKernels per_block_cast_kernel.py, but not identical (current PTO demo hard-codes [32, 32] block while tilelang demo also supports 128 block size)
• The RoPE SIMD VF implementation is similar to CANN/AscendC apply_rotary_pos_emb, but rewritten to be more efficient and take more variants (layouts, modes)

Note on VF performance: With current SIMD VF + optimized GM-level pipelining (tested internally, excluded here), the whole kernel can reach >3.2 TB/s BW on 950DT, thus quite memory-bound, not vector bound (i.e. the VF part is fast). In current demo PR the GM<->UB part is kept naive (single-core, no double buffer pipeline). We will polish and release end-to-end kernel as next step.

Note on syntax/styles: The biggest benefit of vmi is on type casting (abstracts away manual odd-even widening/interleaving/packing). ASC load_store_utils.h tries to abstract similar procedures, but not as elegant.