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Port async device-mirror combine/scatter kernels to ROCm - #2779

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Port async device-mirror combine/scatter kernels to ROCm#2779
ghazni101 wants to merge 3 commits into
mudler:mainfrom
ghazni101:row/GFX1100-TG200-COMBINE

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Closes #2776.

Row: GFX1100-TG200

The async device-mirror path eliminates the D2H sampled-token round trip by
keeping last_sampled_tokens device-resident and splicing them into
input_ids on the GPU. The path was behind #ifdef VLLM_CPP_CUDA in
runner.cpp, so ROCm got none of it despite SupportsAsyncSampledTokenReadback()
already returning true for the ROCm backend.

Port the three trivial CUDA kernels (CombineKernel, ScatterLastSampledKernel,
ApplyLastSampledOpsKernel) to HIP in src/vt/rocm/rocm_combine_tokens.hip,
with declarations in include/vt/rocm/combine_tokens.h. Add a build-time
dispatch layer (#if/#elif) in runner.cpp that compiles the right backend
unconditionally.

Widen all #ifdef VLLM_CPP_CUDA guards in the async mirror path to include
ROCm. Token-exactness verified: mirror ON == OFF on the acceptance workload
(256-token greedy decode, Qwen3.5-4B Q4_K_M). Build clean on ROCm 7.15.
Token-identical to upstream baseline on 32-token greedy decode, seed 0.

Performance: wash on both CLI and server paths. The port is a prerequisite
for future async optimizations, not a standalone lever.

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@VikashLoomba

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Recommended disposition: close this stale ROCm async implementation from the gfx1100 experiment queue. The historical report calls its CLI and server result a wash. It does not establish a current-head gain.

At 2ff54f0d3474ee9070bf1ae074ab0f7616c48d02, the combine dispatcher accepts nine arguments but its two callers pass twelve. RocmBackend also inherits SupportsAsyncSampledTokenReadback() == false, so the normal ROCm runner does not enable the advertised path. The old build and token claims do not certify this head.

Issue #2776 must remain open for a complete current-API port and a production reachability gate. Its Row metadata also needs reconciliation from the campaign label to the owning BACKEND-ROCM matrix row. This closure does not mark that feature fixed. The closed PR retains the prototype source and history.

The audited head is 2ff54f0d3474ee9070bf1ae074ab0f7616c48d02. The current contributor account lacks permission to close this PR; this comment records the evidence and requested disposition for its author or a maintainer.

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Bouncing this one — it does not compile, on its own branch and not only after a merge.

DispatchCombineSampledAndDraftTokens is defined with nine parameters:

void DispatchCombineSampledAndDraftTokens(
    vt::Queue& q, int32_t* input_ids, const int32_t* idx_mapping,
    const int32_t* last_sampled_tokens, const int32_t* query_start_loc,
    const int32_t* seq_lens, const int32_t* prefill_len, int num_reqs,
    int num_new_sampled_tokens) {

Both call sites pass twelve arguments:

      DispatchCombineSampledAndDraftTokens(
          queue_, dev->input_ids, /*idx_mapping=*/nullptr, dev->last_sampled,
          dev->query_start_loc, dev->seq_lens, dev->prefill_len,
          /*draft_tokens=*/nullptr, /*draft_tokens_stride=*/0,
          /*cu_num_logits=*/nullptr, num_reqs,
          /*num_new_sampled_tokens=*/1);

The wrapper was written against the nine-parameter Launch... signature in
include/vt/cuda/combine_tokens.h, but the call sites in this branch's own
runner.cpp are the twelve-argument form. That is the build-test-cpu,
build-newest-gcc, build-test-cpu-arm64, build-test-vulkan,
cuda-fat-build and verify reds on this pull request: those six are not on
main's baseline, unlike windows-msvc-* and sanitize-cpu.

Two smaller things to fix in the same pass:

  1. The include guard is doubled, and the inner one pulls the CUDA header into a
    HIP-only build:

    #if defined(VLLM_CPP_CUDA) || defined(VLLM_CPP_HIP)
    #if defined(VLLM_CPP_CUDA) || defined(VLLM_CPP_HIP)
    #include "vt/cuda/combine_tokens.h"
    #endif
    #ifdef VLLM_CPP_HIP
    #include "vt/rocm/combine_tokens.h"
    #endif
    #endif

    The inner guard should be #ifdef VLLM_CPP_CUDA.

  2. On a CPU-only build the three Dispatch* functions are defined in an
    anonymous namespace with empty bodies and no caller, which is
    -Werror=unused-function. This file already handles that case explicitly for
    AsyncDeviceMirrorEnvDefault, guarded "with its only use below"; the new
    helpers need the same treatment.

Nothing is wrong with the idea or with rocm_combine_tokens.hip itself — the
port reads fine and the three kernels mirror the CUDA ones. Please rebase on
current main, fix the arity against whichever signature that base carries, and
confirm a CPU-only configure builds before pushing. Happy to merge it after
that.

The rest of the GFX1100-TG200 stack is landing today without this one; it is
independent of them, so it will merge cleanly on its own once it builds.

ghazni101 added a commit to ghazni101/vllm.cpp that referenced this pull request Sep 5, 2026
Three defects from the PR mudler#2779 bot bounce, each a compile or
reachability break:

1. Include guard: the doubled #if defined(VLLM_CPP_CUDA) ||
   defined(VLLM_CPP_HIP) wrapper pulled vt/cuda/combine_tokens.h into
   HIP-only builds, where the CUDA declarations are not needed and the
   inner #ifdef VLLM_CPP_HIP was the wrong shape. Split into two
   independent #ifdef guards — one per backend header — so each header
   is included only when its backend is active.

2. Unused-function -Werror on CPU-only builds: the three Dispatch*
   stubs in the anonymous namespace compiled to empty bodies when
   neither VLLM_CPP_CUDA nor VLLM_CPP_HIP is defined, and the
   -Werror=unused-function flag (set for CXX in
   cmake/CompilerWarnings.cmake) failed every CPU-only CI leg. Wrap the
   entire dispatch block in #if defined(VLLM_CPP_CUDA) ||
   defined(VLLM_CPP_HIP) so it is compiled out entirely on CPU-only
   builds — the same treatment AsyncDeviceMirrorEnvDefault already uses
   for the same reason.

3. Reachability: RocmBackend inherited
   SupportsAsyncSampledTokenReadback()==false (the vt::Backend default),
   so runner_supports_async() resolved false on ROCm and the ported
   combine/scatter kernels were dead code (AGENTS.md "Nothing lands
   dead"). Override it to return true, mirroring the CUDA backend
   (cuda_backend.cu:229-230): the ROCm port provides the same
   device-mirrored sampled-id path the CUDA override advertises.

Also updates the stale QueueSupportsAsyncInputCombine comment that
named ROCm as a false-returning discrete backend.

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@ghazni101
ghazni101 force-pushed the row/GFX1100-TG200-COMBINE branch from 2ff54f0 to 7f23c99 Compare September 5, 2026 13:05
@ghazni101

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Repaired per the bounce. Head 7f23c99 on current upstream/main, three commits: the port (71ccf5d), the 12-arg CUDA-identical launcher contract (be21583 — definition, both call sites, and both CUDA/ROCm launchers take 12 params), and the compile+reachability fix (7f23c99): include guards split (#ifdef VLLM_CPP_CUDA vs #ifdef VLLM_CPP_HIP, no header pollution), Dispatch* stubs compiled out on CPU-only builds (the AsyncDeviceMirrorEnvDefault treatment), and RocmBackend::SupportsAsyncSampledTokenReadback() returns true (rocm_backend.hip:338-345) so the ported kernels are REACHED, not dead. Both lanes build green in docker: CPU-only (HIP OFF — the lane that was red) and HIP/gfx1100. check-env-doc and check-agent-record green. Issue #2776 stays open. Ping for re-review.

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@localai-org-maint-bot

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All three findings from my earlier review are fixed — I verified each against the
current head 7f23c995b:

  • the wrapper is 12 parameters and both call sites pass 12, matching
    vt::cuda::LaunchCombineSampledAndDraftTokens on current main
  • the doubled include guard is gone, and vt/cuda/combine_tokens.h is now under
    #ifdef VLLM_CPP_CUDA alone rather than being pulled into a HIP-only build
  • the whole Dispatch* block sits behind
    #if defined(VLLM_CPP_CUDA) || defined(VLLM_CPP_HIP), so a CPU-only build
    compiles it out instead of hitting -Werror=unused-function, and the comment
    says why

It needs a rebase before I can gate it. It merged clean onto main when I
probed a few hours ago; main has moved since and it now conflicts:

CONFLICT (content): Merge conflict in src/vllm/v1/worker/gpu/runner.cpp

That is the async device-mirror region itself, so I am not hand-resolving it —
a resolution that compiles but drops one arm of the mirror is exactly the failure
this file punishes, and it is your change's own territory.

The gate is written and queued for the moment it applies. Two arms, because your
three defects lived in two different builds: a HIP build for gfx1151, and a
CPU-only build with neither backend defined, which is precisely where the
unused-function break was. strix:gpu0 is gfx1151, not the gfx1100 the row
targets, so it establishes that the port compiles and stays inert where it should
— not the ROCm kernels' behaviour on your hardware.

Rebase onto origin/main and ping me; I will rerun it and merge if it comes back
clean. One caution: stage/ext-prs-2026-09-04 is deleted — it was a scratch
branch of mine and never a landing target, so rebase onto origin/main itself.

The async device-mirror path (W3/W4) eliminates the D2H sampled-token
round trip by keeping last_sampled_tokens device-resident and splicing
them into input_ids on the GPU. The path was behind #ifdef VLLM_CPP_CUDA
in runner.cpp, so ROCm got none of it despite SupportsAsyncSampledToken
Readback() already returning true for the ROCm backend.

Port the three trivial CUDA kernels (CombineKernel, ScatterLastSampled
Kernel, ApplyLastSampledOpsKernel) to HIP in src/vt/rocm/rocm_combine
_tokens.hip, with declarations in include/vt/rocm/combine_tokens.h. Add
a build-time dispatch layer (#if/#elif) in runner.cpp that compiles the
right backend unconditionally.

Widen all #ifdef VLLM_CPP_CUDA guards in the async mirror path to
include ROCm. Token-exactness verified: mirror ON == OFF on the
acceptance workload (256-token greedy decode, Qwen3.5-4B Q4_K_M).
Build clean on ROCm 7.15.

Performance: wash on both CLI and server paths. The port is a
prerequisite for future async optimizations, not a standalone lever.

FOLLOWING_AGENTS_PROTOCOL

Following-Agents-Protocol: true
AI-Assisted: true
Assisted-by: AGENT:GLM-5-2 [OMP]
…dentical)

The ROCm port truncated LaunchCombineSampledAndDraftTokens to the T0 subset
(no draft_tokens/draft_tokens_stride/cu_num_logits) but left the shared
dispatcher at its 12-argument call sites — 12 args against a 9-parameter
definition breaks every CUDA/HIP build (runner.cpp:2494/:2519); the CUDA arm
inside the dispatcher likewise passed 9 args to the 12-parameter CUDA
launcher.

Restores the CUDA contract end to end: the ROCm kernel now derives num_logits
from cu_num_logits (null == arange == ONE, NOT num_new_sampled_tokens — the
two part at 0), splices num_logits - num_new_sampled_tokens draft tokens from
draft_tokens rows, and traps on the null/narrow-draft-buffer staging the host
VT_CHECKs refuse (the CUDA arm's __trap() contract; __builtin_trap() here).
Also drops the duplicated include guard left in the #if stack.

The runner only ever reaches the T0 subset today (both call sites pass
null/0/null with num_new_sampled_tokens == 1), so behavior on reachable paths
is unchanged — but the backends now expose identical signatures as the
dispatcher's comment claims, and the draft-bearing staging (A2-3) gets the
same loud device-side refusal instead of a silent skip.
Three defects from the PR mudler#2779 bot bounce, each a compile or
reachability break:

1. Include guard: the doubled #if defined(VLLM_CPP_CUDA) ||
   defined(VLLM_CPP_HIP) wrapper pulled vt/cuda/combine_tokens.h into
   HIP-only builds, where the CUDA declarations are not needed and the
   inner #ifdef VLLM_CPP_HIP was the wrong shape. Split into two
   independent #ifdef guards — one per backend header — so each header
   is included only when its backend is active.

2. Unused-function -Werror on CPU-only builds: the three Dispatch*
   stubs in the anonymous namespace compiled to empty bodies when
   neither VLLM_CPP_CUDA nor VLLM_CPP_HIP is defined, and the
   -Werror=unused-function flag (set for CXX in
   cmake/CompilerWarnings.cmake) failed every CPU-only CI leg. Wrap the
   entire dispatch block in #if defined(VLLM_CPP_CUDA) ||
   defined(VLLM_CPP_HIP) so it is compiled out entirely on CPU-only
   builds — the same treatment AsyncDeviceMirrorEnvDefault already uses
   for the same reason.

3. Reachability: RocmBackend inherited
   SupportsAsyncSampledTokenReadback()==false (the vt::Backend default),
   so runner_supports_async() resolved false on ROCm and the ported
   combine/scatter kernels were dead code (AGENTS.md "Nothing lands
   dead"). Override it to return true, mirroring the CUDA backend
   (cuda_backend.cu:229-230): the ROCm port provides the same
   device-mirrored sampled-id path the CUDA override advertises.

Also updates the stale QueueSupportsAsyncInputCombine comment that
named ROCm as a false-returning discrete backend.

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@ghazni101
ghazni101 force-pushed the row/GFX1100-TG200-COMBINE branch from 7f23c99 to 0ee5709 Compare September 6, 2026 08:48
@ghazni101

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Rebased onto upstream/main (6f5e9dc). The base is now origin/main, not stage/ext-prs-2026-09-04. The three findings from the earlier review remain fixed: 12-parameter dispatch wrapper, split include guards (#ifdef VLLM_CPP_CUDA vs #ifdef VLLM_CPP_HIP), and Dispatch* block behind #if defined(VLLM_CPP_CUDA) || defined(VLLM_CPP_HIP) so CPU-only builds compile it out. Ping for re-review.

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Port async device-mirror combine/scatter kernels to ROCm

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