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196f135
perf/x86/intel: Switch to new Intel CPU model defines
aegl May 20, 2024
f2992e7
perf/x86/intel: Support the 4 new OMR MSRs introduced in DMR and NVL
Jan 14, 2026
0415754
perf/x86/intel: Add support for PEBS memory auxiliary info field in DMR
Jan 14, 2026
bf00265
perf/x86/intel: Add core PMU support for DMR
Jan 14, 2026
c155149
perf/x86: Use macros to replace magic numbers in attr_rdpmc
Jan 14, 2026
65989fb
perf/x86/intel: Add support for rdpmc user disable feature
Jan 14, 2026
528e2d3
perf/x86/intel: Add missing branch counters constraint apply
Feb 28, 2026
a9df039
perf/x86/intel: Fix OMR snoop information parsing issues
Mar 11, 2026
58de257
perf/x86: Fix potential bad container_of in intel_pmu_hw_config
captain5050 Mar 12, 2026
945b7e9
perf/x86/intel: Only check GP counters for PEBS constraints validation
Feb 28, 2026
940962d
perf/x86/intel: Improve validation and configuration of ACR masks
Apr 30, 2026
598f14e
perf/x86/intel: Always reprogram ACR events to prevent stale masks
Apr 30, 2026
fd4d669
perf/x86/intel: Disable PMI for self-reloaded ACR events
Apr 30, 2026
9272635
perf/x86/intel: Enable auto counter reload for DMR
Apr 30, 2026
62f0528
perf/x86/intel: Consolidate MSR_IA32_PERF_CFG_C tracking
Apr 30, 2026
546298c
perf/x86/intel: Extend the ref-cycles event to GP counters
Sep 11, 2023
041f6ee
perf/x86/intel: Update event constraints and cache_extra_regsfor ICX
May 15, 2026
98901a4
perf/x86/intel: Update event constraints and cache_extra_regsfor SPR
May 15, 2026
63baf4c
perf/x86/intel: Update event constraints for DMR
May 15, 2026
cdceb6a
perf/x86/intel: Add Panther Lake support
Apr 15, 2025
54a4ebd
perf/x86/intel: Update event constraints and cache_extra_regsfor ADL
May 15, 2026
7d24abb
perf/x86/intel: Update event constraints and cache_extra_regsfor MTL
May 15, 2026
c2ab686
perf/x86/intel: Update event constraints and cache_extra_regsfor LNL
May 15, 2026
2d463bc
perf/x86/intel: Update event constraints and cache_extra_regsfor ARL
May 15, 2026
05dfbe3
perf/x86/intel: Update event constraints for PTL
May 15, 2026
6ac6064
perf/x86/intel: Update event constraints and cache_extra_regsfor SRF
May 15, 2026
87f2ab9
perf/x86/intel: Update event constraints and cache_extra_regsfor CWF
May 15, 2026
2d4ed16
perf/arm: Drop unused functions
coltonlewis Nov 13, 2024
c4a1ea1
perf/core: Hoist perf_instruction_pointer() and perf_misc_flags()
coltonlewis Nov 13, 2024
6ec0738
perf/powerpc: Use perf_arch_instruction_pointer()
coltonlewis Nov 13, 2024
5f5a049
perf/x86: Refactor misc flag assignments
coltonlewis Nov 13, 2024
d6aea74
perf/core: Correct perf sampling with guest VMs
coltonlewis Nov 13, 2024
ff1d20e
perf/x86/intel: Remove anythread_deprecated bit from perf_capabilities
Jun 16, 2026
317d193
perf/x86/intel: Keep cap_user_rdpmc in sync with RDPMC user-disable s…
Jun 16, 2026
07d0362
perf/x86/intel: Fallback to sw branch type decoding if no hw decoding
Jun 16, 2026
ef199c2
perf/x86/intel: Fix kernel address leakages in LBR stack
Jun 16, 2026
cd1f8d7
perf/x86/intel: Validate the return value of intel_pmu_init_hybrid()
Jun 16, 2026
c28c53b
perf/x86/intel: Drop fixed-counter PEBS constraints for baseline PEBS
Jun 16, 2026
c3f2a2a
perf/core: Fix kernel register info leak via hardware skid
Jun 16, 2026
1bb2639
perf/core: Check kernel access when kernel callchains are requested
Jun 16, 2026
b9ddfb7
perf/x86: Unregister PMI handler on PMU init failure
Jul 17, 2026
2bebd64
perf/x86: Free hybrid state on PMU init failure
Jul 17, 2026
44c3a77
perf/x86: Guard intel_pmu_cpu_dead() against invalid hybrid PMU casts
Jul 17, 2026
a7a93a5
perf/x86/intel: Unwind cpuc state if PEBS buffer setup fails
Jul 17, 2026
dbbf8cd
perf/x86: Remove stale fixed counter helper and fix hybrid PMU access
Jul 17, 2026
560c1f9
perf/x86/intel: Fix intel_cap handling on hybrid PMUs
Jul 17, 2026
e1b5e9d
perf/x86: Optimize ACR handling in match_prev_assignment()
Jul 17, 2026
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44 changes: 44 additions & 0 deletions Documentation/ABI/testing/sysfs-bus-event_source-devices-rdpmc
Original file line number Diff line number Diff line change
@@ -0,0 +1,44 @@
What: /sys/bus/event_source/devices/cpu.../rdpmc
Date: November 2011
KernelVersion: 3.10
Contact: Linux kernel mailing list linux-kernel@vger.kernel.org
Description: The /sys/bus/event_source/devices/cpu.../rdpmc attribute
is used to show/manage if rdpmc instruction can be
executed in user space. This attribute supports 3 numbers.
- rdpmc = 0
user space rdpmc is globally disabled for all PMU
counters.
- rdpmc = 1
user space rdpmc is globally enabled only in event mmap
ioctl called time window. If the mmap region is unmapped,
user space rdpmc is disabled again.
- rdpmc = 2
user space rdpmc is globally enabled for all PMU
counters.

In the Intel platforms supporting counter level's user
space rdpmc disable feature (CPUID.23H.EBX[2] = 1), the
meaning of 3 numbers is extended to
- rdpmc = 0
global user space rdpmc and counter level's user space
rdpmc of all counters are both disabled.
- rdpmc = 1
No changes on behavior of global user space rdpmc.
counter level's rdpmc of system-wide events is disabled
but counter level's rdpmc of non-system-wide events is
enabled.
- rdpmc = 2
global user space rdpmc and counter level's user space
rdpmc of all counters are both enabled unconditionally.

The default value of rdpmc is 1.

Please notice:
- global user space rdpmc's behavior would change
immediately along with the rdpmc value's change,
but the behavior of counter level's user space rdpmc
won't take effect immediately until the event is
reactivated or recreated.
- The rdpmc attribute is global, even for x86 hybrid
platforms. For example, changing cpu_core/rdpmc will
also change cpu_atom/rdpmc.
7 changes: 0 additions & 7 deletions arch/arm/include/asm/perf_event.h
Original file line number Diff line number Diff line change
Expand Up @@ -8,13 +8,6 @@
#ifndef __ARM_PERF_EVENT_H__
#define __ARM_PERF_EVENT_H__

#ifdef CONFIG_PERF_EVENTS
struct pt_regs;
extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
extern unsigned long perf_misc_flags(struct pt_regs *regs);
#define perf_misc_flags(regs) perf_misc_flags(regs)
#endif

#define perf_arch_fetch_caller_regs(regs, __ip) { \
(regs)->ARM_pc = (__ip); \
frame_pointer((regs)) = (unsigned long) __builtin_frame_address(0); \
Expand Down
17 changes: 0 additions & 17 deletions arch/arm/kernel/perf_callchain.c
Original file line number Diff line number Diff line change
Expand Up @@ -96,20 +96,3 @@ perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *re
arm_get_current_stackframe(regs, &fr);
walk_stackframe(&fr, callchain_trace, entry);
}

unsigned long perf_instruction_pointer(struct pt_regs *regs)
{
return instruction_pointer(regs);
}

unsigned long perf_misc_flags(struct pt_regs *regs)
{
int misc = 0;

if (user_mode(regs))
misc |= PERF_RECORD_MISC_USER;
else
misc |= PERF_RECORD_MISC_KERNEL;

return misc;
}
4 changes: 0 additions & 4 deletions arch/arm64/include/asm/perf_event.h
Original file line number Diff line number Diff line change
Expand Up @@ -10,10 +10,6 @@
#include <asm/ptrace.h>

#ifdef CONFIG_PERF_EVENTS
struct pt_regs;
extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
extern unsigned long perf_misc_flags(struct pt_regs *regs);
#define perf_misc_flags(regs) perf_misc_flags(regs)
#define perf_arch_bpf_user_pt_regs(regs) &regs->user_regs
#endif

Expand Down
28 changes: 0 additions & 28 deletions arch/arm64/kernel/perf_callchain.c
Original file line number Diff line number Diff line change
Expand Up @@ -148,31 +148,3 @@ void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry,

arch_stack_walk(callchain_trace, entry, current, regs);
}

unsigned long perf_instruction_pointer(struct pt_regs *regs)
{
if (perf_guest_state())
return perf_guest_get_ip();

return instruction_pointer(regs);
}

unsigned long perf_misc_flags(struct pt_regs *regs)
{
unsigned int guest_state = perf_guest_state();
int misc = 0;

if (guest_state) {
if (guest_state & PERF_GUEST_USER)
misc |= PERF_RECORD_MISC_GUEST_USER;
else
misc |= PERF_RECORD_MISC_GUEST_KERNEL;
} else {
if (user_mode(regs))
misc |= PERF_RECORD_MISC_USER;
else
misc |= PERF_RECORD_MISC_KERNEL;
}

return misc;
}
6 changes: 3 additions & 3 deletions arch/powerpc/include/asm/perf_event_server.h
Original file line number Diff line number Diff line change
Expand Up @@ -101,16 +101,16 @@ struct power_pmu {
int __init register_power_pmu(struct power_pmu *pmu);

struct pt_regs;
extern unsigned long perf_misc_flags(struct pt_regs *regs);
extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
extern unsigned long perf_arch_misc_flags(struct pt_regs *regs);
extern unsigned long perf_arch_instruction_pointer(struct pt_regs *regs);
extern unsigned long int read_bhrb(int n);

/*
* Only override the default definitions in include/linux/perf_event.h
* if we have hardware PMU support.
*/
#ifdef CONFIG_PPC_PERF_CTRS
#define perf_misc_flags(regs) perf_misc_flags(regs)
#define perf_arch_misc_flags(regs) perf_arch_misc_flags(regs)
#endif

/*
Expand Down
2 changes: 1 addition & 1 deletion arch/powerpc/perf/callchain.c
Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,7 @@ perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *re

lr = regs->link;
sp = regs->gpr[1];
perf_callchain_store(entry, perf_instruction_pointer(regs));
perf_callchain_store(entry, perf_arch_instruction_pointer(regs));

if (!validate_sp(sp, current))
return;
Expand Down
2 changes: 1 addition & 1 deletion arch/powerpc/perf/callchain_32.c
Original file line number Diff line number Diff line change
Expand Up @@ -139,7 +139,7 @@ void perf_callchain_user_32(struct perf_callchain_entry_ctx *entry,
long level = 0;
unsigned int __user *fp, *uregs;

next_ip = perf_instruction_pointer(regs);
next_ip = perf_arch_instruction_pointer(regs);
lr = regs->link;
sp = regs->gpr[1];
perf_callchain_store(entry, next_ip);
Expand Down
2 changes: 1 addition & 1 deletion arch/powerpc/perf/callchain_64.c
Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,7 @@ void perf_callchain_user_64(struct perf_callchain_entry_ctx *entry,
struct signal_frame_64 __user *sigframe;
unsigned long __user *fp, *uregs;

next_ip = perf_instruction_pointer(regs);
next_ip = perf_arch_instruction_pointer(regs);
lr = regs->link;
sp = regs->gpr[1];
perf_callchain_store(entry, next_ip);
Expand Down
4 changes: 2 additions & 2 deletions arch/powerpc/perf/core-book3s.c
Original file line number Diff line number Diff line change
Expand Up @@ -2359,7 +2359,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
* Called from generic code to get the misc flags (i.e. processor mode)
* for an event_id.
*/
unsigned long perf_misc_flags(struct pt_regs *regs)
unsigned long perf_arch_misc_flags(struct pt_regs *regs)
{
u32 flags = perf_get_misc_flags(regs);

Expand All @@ -2373,7 +2373,7 @@ unsigned long perf_misc_flags(struct pt_regs *regs)
* Called from generic code to get the instruction pointer
* for an event_id.
*/
unsigned long perf_instruction_pointer(struct pt_regs *regs)
unsigned long perf_arch_instruction_pointer(struct pt_regs *regs)
{
unsigned long siar = mfspr(SPRN_SIAR);

Expand Down
6 changes: 3 additions & 3 deletions arch/s390/include/asm/perf_event.h
Original file line number Diff line number Diff line change
Expand Up @@ -37,9 +37,9 @@ extern ssize_t cpumf_events_sysfs_show(struct device *dev,

/* Perf callbacks */
struct pt_regs;
extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
extern unsigned long perf_misc_flags(struct pt_regs *regs);
#define perf_misc_flags(regs) perf_misc_flags(regs)
extern unsigned long perf_arch_instruction_pointer(struct pt_regs *regs);
extern unsigned long perf_arch_misc_flags(struct pt_regs *regs);
#define perf_arch_misc_flags(regs) perf_arch_misc_flags(regs)
#define perf_arch_bpf_user_pt_regs(regs) &regs->user_regs

/* Perf pt_regs extension for sample-data-entry indicators */
Expand Down
4 changes: 2 additions & 2 deletions arch/s390/kernel/perf_event.c
Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@ static unsigned long instruction_pointer_guest(struct pt_regs *regs)
return sie_block(regs)->gpsw.addr;
}

unsigned long perf_instruction_pointer(struct pt_regs *regs)
unsigned long perf_arch_instruction_pointer(struct pt_regs *regs)
{
return is_in_guest(regs) ? instruction_pointer_guest(regs)
: instruction_pointer(regs);
Expand All @@ -81,7 +81,7 @@ static unsigned long perf_misc_flags_sf(struct pt_regs *regs)
return flags;
}

unsigned long perf_misc_flags(struct pt_regs *regs)
unsigned long perf_arch_misc_flags(struct pt_regs *regs)
{
/* Check if the cpum_sf PMU has created the pt_regs structure.
* In this case, perf misc flags can be easily extracted. Otherwise,
Expand Down
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