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    • SimStm

      Public
      SimStm is a functional verification framework designed for ease of use and clear, intuitive understanding.
      VHDL
      2260Updated Feb 25, 2026Feb 25, 2026
    • Eccelerators docbook5 transform template
      XSLT
      0000Updated Nov 18, 2025Nov 18, 2025
    • EventCatcher is a reusable FPGA component that receives events from user logic and exposes them to software.
      VHDL
      0000Updated Oct 29, 2025Oct 29, 2025
    • Basic vhdl components for eccelerators projects
      HTML
      0000Updated Jul 15, 2025Jul 15, 2025
    • Double Buffer Controller is a reusable FPGA component that alternates between two buffers to provide uninterrupted data flow between hardware modules.
      0000Updated Sep 20, 2024Sep 20, 2024
    • VHDL
      0000Updated Aug 28, 2024Aug 28, 2024
    • Basic eccelerators VHDLpackage
      VHDL
      0000Updated Aug 12, 2024Aug 12, 2024
    • Transform eccelerators setup.py to vivado files
      Python
      0000Updated Apr 30, 2024Apr 30, 2024
    • Generate ANT buildscript to run modelsim from eccelerators setup.py
      Python
      0000Updated Apr 4, 2024Apr 4, 2024
    • Generate ANT buildscript to run ghdl from eccelerators setup.py
      Python
      0000Updated Apr 4, 2024Apr 4, 2024
    • Interrupt Collector is a reusable FPGA component that manages multiple interrupt sources and enables parallel interrupt handling across multi-core processor sys…
      HTML
      0000Updated Apr 4, 2024Apr 4, 2024
    • Interrupt generator as counterpart for simulation test benches and test builds of target devices
      VHDL
      0000Updated Apr 4, 2024Apr 4, 2024
    • Basic ANT build.xml files
      0000Updated Apr 4, 2024Apr 4, 2024
    • Collects junit simulation testcase and selected vivado build results as junit testcase too and merges them to a junitsuites file
      Python
      0000Updated Mar 26, 2024Mar 26, 2024
    • Dispatches consecutive interrupts to different CPU cores
      VHDL
      0000Updated Mar 26, 2024Mar 26, 2024
    • Simple program that splits program listings in a docbook xml file.
      Python
      0000Updated Mar 26, 2024Mar 26, 2024
    • bus-join

      Public
      Join two busses to connect e.g., 2 CPUs to one bus.
      VHDL
      0000Updated Mar 26, 2024Mar 26, 2024
    • CRC Calculator is a reusable FPGA component that computes CRC-32 checksums using the Ethernet polynomial (0x4C11DB7).
      VHDL
      0000Updated Feb 12, 2024Feb 12, 2024
    • Bus dividers as delegates generated by HxS
      JavaScript
      0000Updated Feb 2, 2024Feb 2, 2024
    • SPI Controller is a reusable FPGA component that provides a Serial Peripheral Interface for communication with external SPI devices.
      VHDL
      0000Updated Feb 2, 2024Feb 2, 2024
    • 0000Updated Dec 12, 2023Dec 12, 2023
    • Eccelerators adapted sphinx docbook builder plugin
      Python
      0000Updated Jul 26, 2023Jul 26, 2023
    • Eccelerators sphinx template
      Python
      0000Updated Jul 25, 2023Jul 25, 2023