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#436 fixed incorrect bit width calculation#437

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JayPankajPatel wants to merge 1 commit into
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JayPankajPatel:fix/436_timing-model-bit-width-calc
Open

#436 fixed incorrect bit width calculation#437
JayPankajPatel wants to merge 1 commit into
parallaxsw:masterfrom
JayPankajPatel:fix/436_timing-model-bit-width-calc

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@JayPankajPatel
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Issue

writeBusDcls() in liberty/LibertyWriter.cc computes bit_width incorrectly for ascending bus ranges (e.g. [0:10]).

Root Cause

// before — +1 inside abs(), wrong for ascending ranges
std::abs(dcl->from() - dcl->to() + 1)
// ascending  [0:10]:  abs(0  - 10 + 1) = abs(-9) = 9   ← WRONG
// descending [10:0]:  abs(10 - 0  + 1) = 11             ← correct

// after — +1 outside abs(), correct for both
std::abs(dcl->from() - dcl->to()) + 1
// ascending  [0:10]:  abs(0  - 10) + 1 = 11  ✓
// descending [10:0]:  abs(10 - 0)  + 1 = 11  ✓

Change

One character moved — +1 from inside std::abs() to outside.

Tested against OpenSTA 2.5.0.

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CLAassistant commented May 14, 2026

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2 participants