perf(qwen35): carry the GDN decode state slice in registers across the kv_mem reduction - #1054
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FeathBow merged 1 commit intoSep 18, 2026
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…e kv_mem reduction The gated delta rule decode kernel did its two passes (decay, then rank-1 update) with a global round-trip between them: pass 1 stored the decayed state slice back to global memory, the kv_mem reduction consumed it, and pass 2 reloaded it to apply delta·k and store again. The key slice is only 32 floats per thread and lives in registers across the reduction instead — global memory now sees one read and one write per state element. Measured on 1x A100-40GB vs the pre-change tree (vLLM 0.27.0 baseline, 1024-token prompts, zero failed requests): c16 TPOT 13.51 -> 12.98 ms (-3.9%, output throughput 936 -> 1000 tok/s), bs1 TPOT 9.77 -> 9.36 ms (-4.2%). The kernel's per-layer-step time was 97.0 us vs vLLM's FLA fused_recurrent 43.6 us; the register-carried state removes the extra global round-trip that was the difference from FLA's bandwidth-floor implementation. hf_golden_gate TP1 2/2 (the rewrite is arithmetically identical — same f32 ops in the same order). Signed-off-by: CAICAIIs <3360776475@qq.com>
CAICAIIs
marked this pull request as ready for review
September 17, 2026 11:42
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FeathBow
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Sep 18, 2026
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Summary
The gated delta rule decode kernel did its two passes (decay, then rank-1 update) with a global round-trip between them: pass 1 stored the decayed state slice back to global memory, the kv_mem reduction consumed it, and pass 2 reloaded it to apply delta·k and store again. The key slice is only 32 floats per thread — it lives in registers across the reduction instead, so global memory sees one read and one write per state element.
Measured (1x A100-40GB, vLLM 0.27.0 baseline)
1024-token prompts, greedy,
vllm bench serve, zero failed requests; single run per cell:139d925without perf(qwen35): align the logits GEMM width so the output projection stops landing on an align-1 sm_75 kernel #1046: the cell bundles this change with perf(qwen35): align the logits GEMM width so the output projection stops landing on an align-1 sm_75 kernel #1046's alignment effect at bs1.The kernel's per-layer-step time was 97.0 µs vs vLLM's FLA
fused_recurrent_gated_delta_rule_packed43.6 µs; the register-carried state removes the extra global round-trip that was the difference from FLA's bandwidth-floor implementation. Found via nsys kernel attribution (a fuller doc covering the decode kernel gaps is being prepared separately).Testing
hf_golden_gateTP1 2/2; lib tests 102 passed.Claim boundary
Single-run cells on one GPU; draft pending review. The kernel still has no sm_80 tuning pass; the remaining GDN gap to FLA and the c16 GEMM family deficit (+2.8 ms/step) stay open in the attribution doc's queue.