Similar to chisel's when construct, we can add a method chaining implementation.
reg = Register()
reg.when(io.RESET, init)
.when(io.LOAD, io.I)
.else(4)
If no else case is provided, it could by default wire up the output of the register to the input (so the value doesn't change).
The ordering of the when statements indicate a precedence, so if io.RESET is true, the new value will be init regardless of the value of io.LOAD. This should match the semantics of a simple mux chain implementation.
Similar to chisel's
whenconstruct, we can add a method chaining implementation.If no
elsecase is provided, it could by default wire up the output of the register to the input (so the value doesn't change).The ordering of the
whenstatements indicate a precedence, so ifio.RESETis true, the new value will beinitregardless of the value ofio.LOAD. This should match the semantics of a simple mux chain implementation.