update magma IO syntax

examples/coreir/counters.py

@@ -1,14 +1,14 @@
+import mantle.coreir
+from mantle import *
+from magma import *
 import os
 os.environ['MANTLE'] = 'coreir'
-from magma import *
-from mantle import *
-import mantle.coreir
 
 
 def DefineMantleReg(init):
     class MantleReg(Circuit):
         name = f"MantleReg{init}"
-        IO = ["in", In(Bits(16)), "clk", In(Clock), "out", Out(Bits(16)), "clr", In(Bit)]
+        io = m.IO(in=In(Bits(16)), clk=In(Clock), out=Out(Bits(16)), clr=In(Bit))
         @classmethod
         def definition(io):
             c0 = bits(0, 16)
@@ -25,7 +25,7 @@ def definition(io):
 
 class Counter(Circuit):
     name = "Counter16"
-    IO = ["clk", In(Clock), "clr", In(Bit), "out", Out(Bits(16))]
+    io = m.IO(clk=In(Clock), clr=In(Bit), out=Out(Bits(16)))
 
     @classmethod
     def definition(io):
@@ -35,13 +35,15 @@ def definition(io):
         wire(c1, a.in0)
         wire(r.out, a.in1)
         wire(r.clk, io.clk)
-        wire(a.out, getattr(r, "in"))  # r.in doesn't work because in is a keyword
+        # r.in doesn't work because in is a keyword
+        wire(a.out, getattr(r, "in"))
         wire(r.out, io.out)
         wire(io.clr, r.clr)
 
+
 class Counters(Circuit):
     name = "Counters"
-    IO = ["clk", In(Clock)]
+    io = m.IO(clk=In(Clock))
     @classmethod
     def definition(io):
         count0 = Counter(16)

examples/coreir/counters_wire.py

@@ -1,14 +1,14 @@
+import mantle.coreir
+from mantle import *
+from magma import *
 import os
 os.environ['MANTLE'] = 'coreir'
-from magma import *
-from mantle import *
-import mantle.coreir
 
 
 def DefineMantleReg(init):
     class MantleReg(Circuit):
         name = f"MantleReg{init}"
-        IO = ["in", In(Bits(16)), "clk", In(Clock), "out", Out(Bits(16)), "clr", In(Bit)]
+        io = m.IO(in=In(Bits(16)), clk=In(Clock), out=Out(Bits(16)), clr=In(Bit))
         @classmethod
         def definition(io):
             c0 = bits(0, 16)
@@ -25,7 +25,7 @@ def definition(io):
 
 class Counter(Circuit):
     name = "Counter16"
-    IO = ["clk", In(Clock), "clr", In(Bit), "out", Out(Bits(16))]
+    io = m.IO(clk=In(Clock), clr=In(Bit), out=Out(Bits(16)))
 
     @classmethod
     def definition(io):
@@ -35,21 +35,23 @@ def definition(io):
         wire(c1, a.in0)
         wire(r.out, a.in1)
         wire(r.clk, io.clk)
-        wire(a.out, getattr(r, "in"))  # r.in doesn't work because in is a keyword
+        # r.in doesn't work because in is a keyword
+        wire(a.out, getattr(r, "in"))
         wire(r.out, io.out)
         wire(io.clr, r.clr)
 
+
 class Counters(Circuit):
     name = "Counters_wire"
-    IO = ["clk", In(Clock)]
+    io = m.IO(clk=In(Clock))
     @classmethod
     def definition(io):
         count0_out = DefineWire(16)(name="mywire0")
         count1_out = DefineWire(16)(name="mywire1")
         count0_clr = count1_out.O[8]
         count1_clr = count0_out.O[4]
-        count0 = Counter(16,name="count0")
-        count1 = Counter(16,name="count1")
+        count0 = Counter(16, name="count0")
+        count1 = Counter(16, name="count1")
         count0(
             clk=io.clk,
             out=count0_out.I,

examples/fsm/top.py

@@ -28,7 +28,8 @@ def fsm_logic(current_state: m.Bits(2),
             next_state = State.HBLANK
             next_pixel_count = m.bits(0, 11)
     elif current_state == State.HACT:
-        next_state = State.HBLANK if pixel_count == m.bits(1, 11) else State.HACT
+        next_state = State.HBLANK if pixel_count == m.bits(
+            1, 11) else State.HACT
         # TODO: Support AugAssign node
         # next_pixel_count -= 1
         next_pixel_count = pixel_count - m.uint(1, 11)
@@ -39,11 +40,11 @@ def fsm_logic(current_state: m.Bits(2),
 
 
 class MagmaFSM(m.Circuit):
-    IO = ["frameValid", m.In(m.Bit),
-          "clk", m.In(m.Clock),
-          "rst", m.In(m.AsyncReset),
-          "real_href", m.In(m.Bit),
-          "pixel_valid", m.Out(m.Bit)]
+    io = m.IO(frameValid=m.In(m.Bit),
+              clk=m.In(m.Clock),
+              rst=m.In(m.AsyncReset),
+              real_href=m.In(m.Bit),
+              pixel_valid=m.Out(m.Bit))
 
     @classmethod
     def definition(io):

mantle/common/RAM.py

@@ -6,11 +6,13 @@
 
 __all__ = ["DefineRAM", "DefineDualRAM"]
 
+
 def REGs(n, width, has_ce):
     return [Register(width, has_ce=has_ce) for i in range(n)]
 
+
 def MUXs(n, width):
-    return [Mux(2,width) for i in range(n)]
+    return [Mux(2, width) for i in range(n)]
 
 
 def readport(addr_width, width, regs, raddr):
@@ -35,7 +37,7 @@ def writeport(addr_width, width, regs, WADDR, I, WE):
     n = 1 << addr_width
 
     decoder = Decoder(addr_width)
-    enable = And(2,n)
+    enable = And(2, n)
     enable(decoder(WADDR), repeat(WE, n))
 
     for i in range(n):
@@ -44,49 +46,49 @@ def writeport(addr_width, width, regs, WADDR, I, WE):
 
 def DefineRAM(height, width):
     addr_width = clog2(height)
-    TADDR = Bits[ addr_width ]
-    TDATA = Bits[ width ]
+    TADDR = Bits[addr_width]
+    TDATA = Bits[width]
 
     class _RAM(Circuit):
         name = f'RAM{height}x{width}'
-        IO = ['RADDR', In(TADDR),
-              'RDATA', Out(TDATA),
-              'WADDR', In(TADDR),
-              'WDATA', In(TDATA),
-              'WE', In(Bit),
-              'CLK', In(Clock)
-             ]
+        io = m.IO(RADDR=In(TADDR),
+                  RDATA=Out(TDATA),
+                  WADDR=In(TADDR),
+                  WDATA=In(TDATA),
+                  WE=In(Bit),
+                  CLK=In(Clock)
+                  )
 
         @classmethod
         def definition(io):
             regs = REGs(height, width, has_ce=True)
             writeport(addr_width, width, regs, io.WADDR, io.WDATA, io.WE)
-            wire( readport(addr_width, width, regs, io.RADDR), io.RDATA )
+            wire(readport(addr_width, width, regs, io.RADDR), io.RDATA)
 
     return _RAM
 
 
 def DefineDualRAM(height, width):
     addr_width = clog2(height)
-    TADDR = Bits[ addr_width ]
-    TDATA = Bits[ width ]
+    TADDR = Bits[addr_width]
+    TDATA = Bits[width]
 
     class _DualRAM(Circuit):
         name = f'DualRAM{height}x{width}'
-        IO = ['RADDR0', In(TADDR),
-              'RDATA0', Out(TDATA),
-              'RADDR1', In(TADDR),
-              'RDATA1', Out(TDATA),
-              'WADDR', In(TADDR),
-              'WDATA', In(TDATA),
-              'WE', In(Bit),
-              'CLK', In(Clock)]
+        io = m.IO(RADDR0=In(TADDR),
+                  RDATA0=Out(TDATA),
+                  RADDR1=In(TADDR),
+                  RDATA1=Out(TDATA),
+                  WADDR=In(TADDR),
+                  WDATA=In(TDATA),
+                  WE=In(Bit),
+                  CLK=In(Clock))
 
         @classmethod
         def definition(io):
             regs = REGs(n, width, has_ce=True)
             writeport(addr_width, width, regs, io.WADDR, io.WDATA, io.WE)
-            wire( readport(addr_width, width, regs, io.RADDR0), io.RDATA0 )
-            wire( readport(addr_width, width, regs, io.RADDR1), io.RDATA1 )
+            wire(readport(addr_width, width, regs, io.RADDR0), io.RDATA0)
+            wire(readport(addr_width, width, regs, io.RADDR1), io.RDATA1)
 
     return _DualRAM

mantle/common/ROM.py

@@ -4,26 +4,31 @@
 from mantle import Mux
 from .RAM import readport
 
-__all__  = ['DefineROM', 'ROM']
+__all__ = ['DefineROM', 'ROM']
+
 
 def ROM4(data, i, width):
     return fork([uncurry(LUT(data[i][w], 4)) for w in range(width)])
 
+
 def ROM4s(n, width, data):
     return [ROM4(data, i, width) for i in range(n//16)]
 
+
 def MUXs(n, width):
-    return [Mux(2,width) for i in range(n)]
+    return [Mux(2, width) for i in range(n)]
+
 
 def interleave16(data, width):
     n = len(data)
     bits = [int2seq(data[i], width) for i in range(n)]
     #print(n, bits)
-    data = [ [ [bits[i+j][w] for j in range(16)] for w in range(width)] \
-               for i in range(0,n,16) ]
+    data = [[[bits[i+j][w] for j in range(16)] for w in range(width)]
+            for i in range(0, n, 16)]
     #print(len(data), data)
     return data
 
+
 def DefineROM(height, width, data):
     assert height >= 4
     n = 1 << height
@@ -35,16 +40,16 @@ def DefineROM(height, width, data):
 
     class _ROM(Circuit):
         name = f'ROM{n}x{width}'
-        IO = ['RADDR', In(TADDR), 'RDATA', Out(TDATA)]
+        io = m.IO(RADDR=In(TADDR), RDATA=Out(TDATA))
 
         @classmethod
         def definition(io):
             roms = ROM4s(n, width, data)
             [roms[i](io.RADDR[0:4]) for i in range(n//16)]
-            wire( readport(height-4, width, roms, io.RADDR[4:]), io.RDATA )
+            wire(readport(height-4, width, roms, io.RADDR[4:]), io.RDATA)
 
     return _ROM
 
+
 def ROM(height, width, data=None):
     return DefineROM(height, width, data=data)()
-

mantle/common/arbiter.py

@@ -8,24 +8,30 @@
 # an Arbiter returns an array with only a single bit set,
 # in this case the lowest bit set is retained
 #
+
+
 def DefineArbiter(n):
-    T = Bits[ n ]
+    T = Bits[n]
+
     class _Arbiter(Circuit):
         name = 'Arbiter'+str(n)
-        IO = ['I', In(T), 'O', Out(T)]
+        io = m.IO(I=In(T), O=Out(T))
         @classmethod
         def definition(Arb):
             ones = n * [1]
             y = DefineAdd(n)()(Arb.I, array(ones))  # y = x - 1
+
             def a(y):
-                return LUT([0, 1, 0, 0]) # A0 & ~A1
+                return LUT([0, 1, 0, 0])  # A0 & ~A1
             arb = join(col(a, n))
             arb(Arb.I, y)
             wire(arb.O, Arb.O)
     return _Arbiter
 
+
 def Arbiter(n, **kwargs):
     return DefineArbiter(n)(**kwargs)
 
+
 def arbiter(I, **kwargs):
     return Arbiter(len(I), **kwargs)(I)