-
-
Notifications
You must be signed in to change notification settings - Fork 72
Issues
is:issue state:open
is:issue state:open
Issue creation is restricted in this repository
Search results
Inconsistency between Verilog Maths and Python Fixed-Point Model
bugSomething isn't workingSomething isn't workingStatus: Open.#167 In projf/projf-explore;Support SPRAM Framebuffer
enhancementNew feature or requestNew feature or requestStatus: Open.#133 In projf/projf-explore;UART echo's back half the input
bugSomething isn't workingSomething isn't workingStatus: Open.#131 In projf/projf-explore;Remove Old Clock Gen Modules
enhancementNew feature or requestNew feature or requestStatus: Open.#123 In projf/projf-explore;Colour Index Latency Correction with bitmap_addr
bugSomething isn't workingSomething isn't workingStatus: Open.#115 In projf/projf-explore;Sub-Pixel Drawing Precision
enhancementNew feature or requestNew feature or requestStatus: Open.#113 In projf/projf-explore;Shared Triangle Edges
enhancementNew feature or requestNew feature or requestStatus: Open.#112 In projf/projf-explore;Triangle outline and fill not congruent
bugSomething isn't workingSomething isn't workingStatus: Open.#111 In projf/projf-explore;Verilator/SDL Screen Array Unchecked (C++)
bugSomething isn't workingSomething isn't workingStatus: Open.#90 In projf/projf-explore;