Support for outstanding HCI transactions

Bender.yml

@@ -46,6 +46,11 @@ sources:
       - rtl/ecc/hci_ecc_dec.sv
       - rtl/ecc/hci_ecc_enc.sv
       - rtl/ecc/hci_ecc_manager.sv
+      - rtl/outstanding/hci_outstanding_assign.sv
+      - rtl/outstanding/hci_outstanding_mux.sv
+      - rtl/outstanding/hci_outstanding_rob.sv
+      - rtl/outstanding/hci_outstanding_source.sv
+      - rtl/outstanding/hci_outstanding_fifo.sv
       - rtl/interco/hci_log_interconnect.sv
       - rtl/interco/hci_log_interconnect_l2.sv
       - rtl/interco/hci_new_log_interconnect.sv # `new_XBAR_TCDM` dep. is a private repo
@@ -57,6 +62,7 @@ sources:
       # Level 3
       - rtl/core/hci_core_sink.sv
       - rtl/ecc/hci_ecc_source.sv
+      - rtl/outstanding/hci_outstanding_sink.sv
       - rtl/interco/hci_router.sv
       # Level 4
       - rtl/ecc/hci_ecc_interconnect.sv

rtl/common/hci_helpers.svh

@@ -245,6 +245,17 @@
   // Asserts (specialized definition for conventional param names
   `define HCI_SIZE_CHECK_ASSERTS(__intf) `HCI_SIZE_CHECK_ASSERTS_EXPLICIT_PARAM(`HCI_SIZE_PARAM(__intf), __intf)
 
+  // Asserts (generic definition usable with any parameter name)
+  `define HCI_OUTSTANDING_SIZE_CHECK_ASSERTS_EXPLICIT_PARAM(__xparam, __xintf) \
+  initial __xparam``_intf_size_check_dw  : assert(__xparam.DW  == `HCI_SIZE_GET_DW_CHECK(__xintf)); \
+  initial __xparam``_intf_size_check_bw  : assert(__xparam.BW  == `HCI_SIZE_GET_BW_CHECK(__xintf)); \
+  initial __xparam``_intf_size_check_aw  : assert(__xparam.AW  == `HCI_SIZE_GET_AW_CHECK(__xintf)); \
+  initial __xparam``_intf_size_check_uw  : assert(__xparam.UW  == `HCI_SIZE_GET_UW_CHECK(__xintf)); \
+  initial __xparam``_intf_size_check_iw  : assert(__xparam.IW  == `HCI_SIZE_GET_IW_CHECK(__xintf));
+
+  // Asserts (specialized definition for conventional param names
+  `define HCI_OUTSTANDING_SIZE_CHECK_ASSERTS(__intf) `HCI_OUTSTANDING_SIZE_CHECK_ASSERTS_EXPLICIT_PARAM(`HCI_SIZE_PARAM(__intf), __intf)
+
 `endif
 
 `endif /* `ifndef __HCI_HELPERS__ */

rtl/common/hci_interfaces.sv

@@ -1,6 +1,7 @@
 /*
  * hci_interfaces.sv
  * Francesco Conti <f.conti@unibo.it>
+ * Marco Bertuletti <mbertuletti@iis.ee.ethz.ch>
  *
  * Copyright (C) 2019-2020 ETH Zurich, University of Bologna
  * Copyright and related rights are licensed under the Solderpad Hardware
@@ -207,6 +208,91 @@ interface hci_core_intf (
 
 endinterface // hci_core_intf
 
+interface hci_outstanding_intf (
+  input logic clk
+);
+
+  import hci_package::*;
+
+  parameter int unsigned DW  = hci_package::DEFAULT_DW;  /// Data Width
+  parameter int unsigned AW  = hci_package::DEFAULT_AW;  /// Address Width
+  parameter int unsigned BW  = hci_package::DEFAULT_BW;  /// Width of a "byte" in bits (default 8)
+  parameter int unsigned UW  = hci_package::DEFAULT_UW;  /// User Width
+  parameter int unsigned IW  = hci_package::DEFAULT_IW;  /// ID Width
+
+  // handshake signals
+  logic req_valid;
+  logic req_ready;
+  logic resp_valid;
+  logic resp_ready;
+
+  // request phase payload
+  logic [AW-1:0]    req_add;
+  logic             req_wen; // wen=1'b1 for LOAD, wen=1'b0 for STORE
+  logic [DW-1:0]    req_data;
+  logic [DW/BW-1:0] req_be;
+  logic [hci_package::iomsb(UW):0] req_user;
+  logic [hci_package::iomsb(IW):0] req_id;
+
+  // response phase payload
+  logic [DW-1:0] resp_data;
+  logic [hci_package::iomsb(UW):0] resp_user;
+  logic [hci_package::iomsb(IW):0] resp_id;
+  logic resp_opc;
+
+  modport initiator (
+    output req_add,
+    output req_wen,
+    output req_data,
+    output req_be,
+    output req_user,
+    output req_id,
+    output req_valid,
+    input  req_ready,
+    input  resp_data,
+    input  resp_user,
+    input  resp_id,
+    input  resp_opc,
+    input  resp_valid,
+    output resp_ready
+  );
+
+  modport target (
+    input  req_add,
+    input  req_wen,
+    input  req_data,
+    input  req_be,
+    input  req_user,
+    input  req_id,
+    input  req_valid,
+    output req_ready,
+    output resp_data,
+    output resp_user,
+    output resp_id,
+    output resp_opc,
+    output resp_valid,
+    input  resp_ready
+  );
+
+  modport monitor (
+    input req_add,
+    input req_wen,
+    input req_data,
+    input req_be,
+    input req_user,
+    input req_id,
+    input req_valid,
+    input req_ready,
+    input resp_data,
+    input resp_user,
+    input resp_id,
+    input resp_opc,
+    input resp_valid,
+    input resp_ready
+  );
+
+endinterface // hci_outstanding_intf
+
 `ifdef BUILD_DEPRECATED
 interface hci_mem_intf (
   input logic clk

rtl/outstanding/hci_outstanding_assign.sv

@@ -0,0 +1,45 @@
+/*
+ * hci_outstanding_assign.sv
+ * Marco Bertuletti <mbertuletti@iis.ee.ethz.ch>
+ *
+ * Copyright (C) 2019-2020 ETH Zurich, University of Bologna
+ * Copyright and related rights are licensed under the Solderpad Hardware
+ * License, Version 0.51 (the "License"); you may not use this file except in
+ * compliance with the License.  You may obtain a copy of the License at
+ * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+ * or agreed to in writing, software, hardware and materials distributed under
+ * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+ * CONDITIONS OF ANY KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations under the License.
+ */
+
+/**
+ * The **hci_outstanding_assign** module implements a simple assignment for
+ * HCI-Outstanding streams.
+ *
+ */
+
+module hci_outstanding_assign 
+  import hwpe_stream_package::*;
+(
+  hci_outstanding_intf.target    tcdm_target,
+  hci_outstanding_intf.initiator tcdm_initiator
+);
+
+  assign tcdm_initiator.req_add     = tcdm_target.req_add;
+  assign tcdm_initiator.req_wen     = tcdm_target.req_wen;
+  assign tcdm_initiator.req_data    = tcdm_target.req_data;
+  assign tcdm_initiator.req_be      = tcdm_target.req_be;
+  assign tcdm_initiator.req_user    = tcdm_target.req_user;
+  assign tcdm_initiator.req_id      = tcdm_target.req_id;
+  assign tcdm_initiator.req_valid   = tcdm_target.req_valid;
+  assign tcdm_target.req_ready      = tcdm_initiator.req_ready;
+
+  assign tcdm_target.resp_data     = tcdm_initiator.resp_data;
+  assign tcdm_target.resp_user     = tcdm_initiator.resp_user;
+  assign tcdm_target.resp_id       = tcdm_initiator.resp_id;
+  assign tcdm_target.resp_opc      = tcdm_initiator.resp_opc;
+  assign tcdm_target.resp_valid    = tcdm_initiator.resp_valid;
+  assign tcdm_initiator.resp_ready = tcdm_target.resp_ready;
+
+endmodule // hci_outstanding_assign