[ET-VK] Fix softmax NaN and depthwise conv correctness bugs#17861
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Fix three bugs causing incorrect output when running the edgeTAM model
with the Vulkan backend. Together these fixes bring the model from
producing all-NaN output to matching the reference within fp32 tolerance.
**Bug 1 — softmax_packed_dim OOB max contamination (softmax.glsl)**
In `softmax_packed_dim`, each workgroup uses NWORKERS=4 threads to
collaboratively reduce along the packed dimension. Before the main loop,
each worker initializes `max_elements` by loading from texel index
`tid.x`. When NWORKERS exceeds the number of texels (e.g., a 12-element
dim has only 3 texels, but worker 3 tries to load texel index 3), the
load is out-of-bounds and returns 0 per Vulkan spec. This 0 enters the
cross-worker max reduction, so for any row where all actual values are
negative, the computed max becomes 0 instead of the true (negative) max.
Then `exp(value - 0)` underflows to 0 for all elements, giving
denominator=0 and NaN output.
Fixed by initializing `max_elements = vec4(-3.402823e+38)` (i.e.,
-FLT_MAX) so that workers with no valid texels contribute -inf to the
reduction. Also added a `safe_denominator = max(denominator, 1e-37)`
clamp as a secondary safety net against any remaining underflow edge
cases.
This affected the edgeTAM attention softmax over 12 key positions, where
~15% of query rows had all-negative attention scores and produced NaN.
**Bug 1b — softmax_nonpacked_dim defensive hardening (softmax.glsl)**
Applied similar defensive fixes to `softmax_nonpacked_dim`:
- Clamped denominator via `max(denominators, vec4(1e-37))` to prevent
0/0 = NaN if all exp values underflow.
- Added IEEE 754 bit-level NaN/Inf → 0 sanitization on output texels.
This uses `floatBitsToUint`/`uintBitsToFloat` with exponent-bit
masking rather than `isnan()` or `x != x`, which may not work reliably
on all GPU drivers due to OpIsNan bugs and ordered comparison
semantics.
- Added `memoryBarrierImage()` after the output write loop to flush
imageStore writes so they're visible to subsequent GPU operations.
**Bug 2 — conv2d_dw parameter binding mismatch (Convolution.cpp)**
The depthwise convolution code path in `add_conv2d_node` unconditionally
passed kernel parameters (stride, padding, dilation, etc.) via push
constants. However, the base `conv2d_dw.glsl` shader (used for non-3x3
and non-5x5 kernels, such as 1x1 depthwise convolutions) declares these
parameters as UBOs at binding points 4–8, not as push constants. The
`_output_tile` shader variants do use push constants, so 3x3 and 5x5
depthwise convolutions worked correctly.
For 1x1 depthwise convolutions, the shader read from unbound UBOs,
getting zeros for stride, padding, dilation, and overlay_region. With
stride=0 and overlay_region=(0,0), the convolution loop never executed,
producing output equal to just the bias (effectively zero for small
biases).
Fixed by checking whether the selected shader name contains
`_output_tile`. If not, parameters are passed via UBOs (matching the
shader's declarations) instead of push constants.
**Bug 3 — conv2d_dw workgroup size mismatch (Convolution.cpp)**
The base `conv2d_dw.glsl` shader uses a fully 1D thread mapping where
`gl_GlobalInvocationID.x` encodes all three output dimensions:
`pos.x = gid.x % W`, `pos.y = (gid.x / W) % H`,
`pos.z = gid.x / (W * H)`. The `_output_tile` variants use a 2D mapping
with spatial tiles in `.x` and channels in `.y`.
The `conv2d_global_wg_size` callback was dispatching all depthwise
shaders with workgroup size `{W*H, C_packed, 1}`, which is correct for
`_output_tile` but wrong for the base shader. With this size, all
threads have `gid.x < W*H`, so `pos.z = gid.x / (W*H) = 0` — only
channel texel 0 (channels 0–3 out of e.g. 192) gets computed.
Fixed by dispatching `{W*H*C_packed, 1, 1}` for the base shader so
that `gid.x` ranges over all spatial × channel positions.
Differential Revision: [D95217947](https://our.internmc.facebook.com/intern/diff/D95217947/)
ghstack-source-id: 347411472
Pull Request resolved: #17848
🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/17861
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Two bugs caused incorrect outputs in models with mixed-dtype binary operations (e.g. EdgeTAM remaining frames): 1. Mixed-dtype binary ops (e.g. int arange vs float tensor) were fed to shaders that declare both inputs with the same DTYPE, causing data misinterpretation. This is now fixed by adding an `InsertDtypePromotionPass` export pass that inserts `_to_copy` nodes to promote inputs to a common dtype at compile time. The `_to_copy` op is extended to support int<->float conversions via new `view_convert_texture` shaders, and the previous float/half-only restriction in ToCopy.cpp is replaced with branching logic that uses BlitNode for same-dtype/float<->half and view_convert shaders for other conversions. 2. Texture3d comparison operators (gt, lt, le, ge, eq) used `all()` to reduce component-wise `bvec4` results to a single bool. With packed textures where padding components are zero, `all()` always returned false because padding zeros fail comparison against non-zero values. Fixed by removing `all()` so the result stays as a component-wise `bvec4`, which is correctly converted to `uvec4` for the Bool output texture. Additional changes: - New `view_convert_texture.glsl` shader and YAML for texture dtype conversion - `add_view_copy_convert_texture_node` added to View.cpp/h - `_to_copy` op registry updated to accept int dtypes (FP_INT_T) Differential Revision: [D95217948](https://our.internmc.facebook.com/intern/diff/D95217948/) ghstack-source-id: 347411474 Pull Request resolved: #17849
…g ops The insert_prepack_nodes pass was skipping prepack node insertion for all constant tensor args of ops with supports_prepacking=True. However, these ops only handle prepacking for weight/bias tensors internally; the primary input tensor is still expected to be a GPU tensor. If the primary input happens to be a constant tensor (serialized as TensorRef), the op throws an exception at runtime. Fix this by detecting the primary input index directly in insert_prepack_nodes. Most prepacking ops have the primary input at arg 0, but embedding uses arg 1 since its signature is embedding(weight, indices, ...). The pass now checks whether a constant tensor is used as the primary input of a prepacking op, and if so, still inserts a prepack node for it. Differential Revision: [D95217949](https://our.internmc.facebook.com/intern/diff/D95217949/) ghstack-source-id: 347411473 Pull Request resolved: #17850
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Mar 5, 2026
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This PR was created by the merge bot to help merge the original PR into the main branch.
ghstack PR number: #17848 by @SS-JIA
^ Please use this as the source of truth for the PR details, comments, and reviews
ghstack PR base: https://github.com/pytorch/executorch/tree/gh/SS-JIA/457/base
ghstack PR head: https://github.com/pytorch/executorch/tree/gh/SS-JIA/457/head
Merge bot PR base: https://github.com/pytorch/executorch/tree/main
Merge bot PR head: https://github.com/pytorch/executorch/tree/gh/SS-JIA/457/orig
Differential Revision: D95217947
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