Senior EDA software engineer focused on chip implementation flows, physical verification, chip test automation, and verification infrastructure.
- EDA Flow Engineering
- APR / Physical Implementation Flow
- Tcl-based EDA Automation
- Physical Verification
- Chip Test Automation
- JTAG / ATE / WGL / Testbench Infrastructure
- Safe-IC Verification Platform
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eda-flow-engineering-practice
Notes on reproducible EDA runtime environments, session models, Tcl automation, logs, and flow infrastructure. -
chip-test-automation-notes
Notes on JTAG vector generation, VCD-to-WGL conversion, WGL integration, and synthesizable testbench generation.
I write about EDA engineering from the perspective of system structure, automation, reproducibility, and tool infrastructure.