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1. CORDIC_FPGA CORDIC_FPGA Public

   CORDIC implementation on FPGA. This repo includes the src files and utilization report, including the embedded system for the 7 segment displays on the Nexys 4 DDR FPGA

   Verilog

2. OoO-Precise-RV32G OoO-Precise-RV32G Public

   Pipelined RISC-V CPU with Out of Order Execution, custom bitcodes for AXI burst reading and writing and square root and inverse square root, and full cache and DRAM connectivity implementation

   Verilog

3. Pong-on-LC3 Pong-on-LC3 Public

   Pong on a novel 16 bit LC-3 multi cycle design with memory for the same, along with VGA module for screen interfacing.

   Verilog

4. RISC-V-CPU RISC-V-CPU Public

   Novel RISC V CPU single cycle design in the 32 bit ISA

   Verilog