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raviranjan-vlsi/README.md

Hi 👋, I'm Raviranjan Kumar

A passionate VLSI Engineer from India

  • 🔭 I’m currently working on Implementation of AHB Master - Slave and verification using system Verilog and UVM

  • 🌱 I’m currently learning DSA, UVM

  • 👨‍💻 All of my projects are available at https://www.linkedin.com/in/raviranjan-kumar-ece/

  • 💬 Ask me about Verilog , System Verilog , CDC , FIFO, AMBA

  • 📫 How to reach me raviranjan.kumar.ece@gmail.com

  • ⚡ Fun fact I Think I am Very Blessed

Connect with me:

https://www.linkedin.com/in/raviranjan-kumar-ece/

Languages and Tools:

arduino c cplusplus git linux perl python

raviranjan-vlsi

 raviranjan-vlsi

raviranjan-vlsi

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