🎯 FPGA Oscilloscope with VGA Output — DE10-Lite

A fully functional digital oscilloscope implemented on the Intel/Altera DE10-Lite FPGA using VHDL, displaying real-time analog signals via VGA output.

Oscilloscope waveform displayed in real-time via VGA

✅ Live visualization of electrical signals from ADC
🎨 640x480 VGA display with waveform & grid
🔁 Smooth scrolling visualization
📟 Optional debug with 7-segment displays

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📸 Project in Action

Application example: EMG signal acquisition and visualization

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🧠 Project Structure

The oscilloscope is composed of three main VHDL modules:

🔹 top.vhd

Integrates all submodules:

• Connects the ADC acquisition logic (adc_teste)
• Sends processed data to VGA renderer (vga_teste)
• Optionally outputs debug data to 7-segment displays

🔹 adc_teste.vhd

Simulates analog signal acquisition:

• Uses a simulated 12-bit ADC (adcteste)
• Converts sampled analog voltage into digital values
• Controls sampling frequency via a clock divider
• Displays current ADC value on HEX0–HEX2 (optional)

🔹 vga_teste.vhd

Draws waveforms on the VGA screen:

• Implements 640×480 @ 60Hz VGA timing
• Scales incoming 12-bit samples to vertical resolution
• Continuously scrolls waveform left to right
• Overlays a grid every 64px (horizontal) and 48px (vertical)
• Colors:
  • 🟩 Waveform: green
  • ⬛ Background: black
  • 🟥 Grid: dark gray

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🧩 How It Works

1. Sampling (ADC)

   • The FPGA samples analog signals using a simulated adcteste module (can be replaced by a real ADC module if desired).
   • Sampling clock is generated by dividing the 50MHz system clock to match ~1MHz rate.

2. Buffering

   • A circular buffer stores the last 640 samples.
   • Another buffer (display_buffer) shifts samples to simulate scrolling across the screen.

3. VGA Rendering

   • At 25MHz (half the system clock), pixels are drawn on screen.
   • The waveform is rendered by scaling the 12-bit sample to 480 vertical pixels.
   • Wave points are drawn with ±2 pixel thickness for visibility.
   • Gridlines are overlaid for signal analysis.

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🔧 Getting Started

Requirements

• Intel Quartus Prime
• Intel DE10-Lite FPGA Board
• VGA Monitor and cable

Compilation Steps

1. Clone or download this repository.
2. Open top.vhd as the top-level entity in Quartus.
3. Assign appropriate FPGA pins (this doesn't need to be done if you use the Golden-Top file):
   • VGA (R/G/B, HS, VS)
   • 7-segment display (HEX0–HEX2)
4. Compile and program the FPGA.
5. Connect analog signal to CH0 of ADC input.
6. Observe real-time waveform on VGA screen.

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📦 File Overview

File	Description
top.vhd	Top-level integration of ADC and VGA modules
adc_teste.vhd	Simulates ADC sampling and drives display digits
vga_teste.vhd	VGA driver that scrolls and plots waveform
application.gif	Recording of real use with EMG signals
osc.gif	VGA output showing waveform rendering

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🧠 Possible Improvements

• Add functionality to change voltage or time subdivisions with external control
• Replace adcteste with external SPI/I²C ADC module
• Add trigger level and sweep modes
• Integrate UART/USB for signal export
• Add menu overlays and multiple channels

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👨‍🔬 Applications

• Biomedical signal monitoring (e.g., EMG, ECG)
• Educational visualization of analog signals
• Embedded system debugging
• Sensor signal inspection

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🙌 Acknowledgments

This project was developed as the final assignment for the Reconfigurable Computing course in my Electronics Engineering degree program. It showcases the practical application of VHDL, FPGA-based signal processing, and VGA output for real-time analog signal visualization.

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📚 Sources

Videos created by Dr. Felipe Pfrimer, my professor in the Reconfigurable Computing class, demonstrating key concepts used in this project:

🎥 Operate VGA port with VHDL and FPGA
🎥 Using the ADC of the DE-10 Lite kit

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