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LICENSE
LICENSE
 
 
Makefile
Makefile
 
 
README.md
README.md
 
 
bits.c
bits.c
 
 
bits.h
bits.h
 
 
cache.c
cache.c
 
 
fib_rec_c.c
fib_rec_c.c
 
 
fib_rec_s.s
fib_rec_s.s
 
 
find_max_index_c.c
find_max_index_c.c
 
 
find_max_index_s.s
find_max_index_s.s
 
 
get_bitseq_c.c
get_bitseq_c.c
 
 
get_bitseq_s.s
get_bitseq_s.s
 
 
int_to_str_c.c
int_to_str_c.c
 
 
int_to_str_s.s
int_to_str_s.s
 
 
is_pal_rec_c.c
is_pal_rec_c.c
 
 
is_pal_rec_s.s
is_pal_rec_s.s
 
 
max3_c.c
max3_c.c
 
 
max3_s.s
max3_s.s
 
 
midpoint_c.c
midpoint_c.c
 
 
midpoint_s.s
midpoint_s.s
 
 
project04.c
project04.c
 
 
project04.h
project04.h
 
 
quadratic_c.c
quadratic_c.c
 
 
quadratic_s.s
quadratic_s.s
 
 
rv_emu.c
rv_emu.c
 
 
rv_emu.h
rv_emu.h
 
 
sort_c.c
sort_c.c
 
 
sort_s.s
sort_s.s
 
 
str_to_int_c.c
str_to_int_c.c
 
 
str_to_int_s.s
str_to_int_s.s
 
 
to_upper_c.c
to_upper_c.c
 
 
to_upper_s.s
to_upper_s.s
 
 
verbose.c
verbose.c
 
 

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RISC-V Emulator

This repository contains a RISC-V emulator with an integrated cache simulation module designed to explore the impact of caching on instruction execution and performance.

Features

  • Emulator: Simulates RISC-V architecture instructions.
  • Cache Simulation: Analyzes the effect of caching on performance.

Technologies

  • Written in C and Assembly.
  • Uses Makefile for build automation.

Warning

For academic honesty, do not replicate or use this code for coursework or assessments.

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RISC-V emulator integrated with a cache simulation module to explore the impact of caching on instruction execution and performance.

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MIT license
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