C166 rzil

librz/arch/cpus/c166-c166-generic.sdb.txt

@@ -37,9 +37,9 @@ IDX1.comment=MAC Address Pointer 1
 ADEIC=io
 ADEIC.address=0xff9a
 ADEIC.comment=A/D Converter Overrun Error Interrupt Control Register
-SYSCON=io
-SYSCON.address=0xff0c
-SYSCON.comment=CPU System Configuration Register
+BUSCON0=io
+BUSCON0.address=0xff0c
+BUSCON0.comment=Bus Configuration Register 0 (Stack Pointer Segment Register [SPSEG])
 VECSEG=io
 VECSEG.address=0xff12
 VECSEG.comment=Bus Configuration Register 0
@@ -313,9 +313,6 @@ CCM7.comment=CAPCOM Mode Control Register 7
 CP=io
 CP.address=0xfe10
 CP.comment=CPU Context Pointer Register
-R1=io
-R1.address=0xfe12
-R1.comment=General Purpose Word Register R1
 CRIC=io
 CRIC.address=0xff6a
 CRIC.comment=GPT2 CAPREL Interrupt Ctrl. Register

librz/arch/filter.c

@@ -6,7 +6,9 @@
 #include <rz_type.h>
 #include <rz_util.h>
 #include <rz_arch.h>
+#include <rz_parse.h>
 #include "analysis_private.h"
+#include "rz_analysis.h"
 
 #define isx86separator(x) ( \
 	(x) == ' ' || (x) == '\t' || (x) == '\n' || (x) == '\r' || (x) == ' ' || \
@@ -209,6 +211,12 @@ static bool filter(RzParse *p, ut64 addr, RzFlag *f, RzAnalysisHint *hint, char
 	ut64 off;
 	bool x86 = false;
 	bool arm = false;
+	bool c16x = false;
+	if (p && p->analb.analysis) {
+		if (strstr(p->analb.analysis->cur->arch, "c166")) {
+			c16x = true;
+		}
+	}
 	if (p && p->cur && p->cur->name) {
 		if (strstr(p->cur->name, "x86")) {
 			x86 = true;
@@ -445,7 +453,7 @@ static bool filter(RzParse *p, ut64 addr, RzFlag *f, RzAnalysisHint *hint, char
 				}
 			}
 		}
-		if (hint) {
+		if (hint && !c16x) {
 			char *num_start = ptr;
 			char *num_end = ptr2;
 			const int nw = hint->nword;

librz/arch/isa/c166/c166_common.c

@@ -0,0 +1,69 @@
+// SPDX-FileCopyrightText: 2025-2026 Sergey Sharshunov <s.sharshunov@gmail.com>
+// SPDX-License-Identifier: LGPL-3.0-only
+
+#include "c166/c166_common.h"
+
+const char *const c166_rw[] = {
+	"r0", "r1", "r2", "r3",
+	"r4", "r5", "r6", "r7",
+	"r8", "r9", "r10", "r11",
+	"r12", "r13", "r14", "r15",
+};
+
+const char *const c166_rb[] = {
+	"rl0", "rh0",
+	"rl1", "rh1",
+	"rl2", "rh2",
+	"rl3", "rh3",
+	"rl4", "rh4",
+	"rl5", "rh5",
+	"rl6", "rh6",
+	"rl7", "rh7",
+};
+
+/**
+ * Maps hexcodes to condition codes for JMPR instructions
+ * Used to determine the condition code for conditional jump instructions
+ */
+// C166 condition code names
+// static
+const char *const conds_names[] = {
+	[C166_CC_UC]    = "cc_UC",      ///< Unconditional
+	[C166_CC_V]     = "cc_V",       ///< Overflow
+	[C166_CC_NV]    = "cc_NV",      ///< No Overflow
+	[C166_CC_N]     = "cc_N",       ///< Negative
+	[C166_CC_NN]    = "cc_NN",      ///< Not Negative
+	[C166_CC_C]     = "cc_C/ULT",   ///< Carry
+	[C166_CC_NC]    = "cc_NC/UGE",  ///< No Carry
+	[C166_CC_EQ]    = "cc_Z/EQ",    ///< Equal
+	[C166_CC_NE]    = "cc_NZ/NE",   ///< Not Equal
+	[C166_CC_ULE]   = "cc_ULE",     ///< Unsigned Less Than or Equal
+	[C166_CC_UGT]   = "cc_UGT",     ///< Unsigned Greater Than
+	[C166_CC_SLE]   = "cc_SLE",     ///< Signed Less Than or Equal
+	[C166_CC_SGE]   = "cc_SGE",     ///< Signed Greater Than or Equal
+	[C166_CC_SGT]   = "cc_SGT",     ///< Signed Greater Than
+	[C166_CC_NET]   = "cc_NET",     ///< Not Equal and Not End-of-Table
+
+	[C166_CC_SLT]   = "cc_SLT",     ///< Signed Less Than
+
+	[C166_CC_NUSR0] = "cc_NUSR0",   ///< USR-bit 0 is cleared (*)
+	[C166_CC_NUSR1] = "cc_NUSR1",   ///< USR-bit 1 is cleared (*)
+	[C166_CC_USR0]  = "cc_USR0",    ///< USR-bit 0 is set 1
+	[C166_CC_USR1]  = "cc_USR1"     ///< USR-bit 1 is set 1
+};
+// clang-format on
+
+const char *conds(ut8 cc) {
+	return conds_names[cc << 1];
+}
+
+const char *conds_extended(ut8 cc) {
+	return conds_names[cc];
+}
+
+const char *const c166_extx_names[] = {
+	"exts",
+	"extp",
+	"extsr",
+	"extpr"
+};

librz/arch/isa/c166/c166_common.h

@@ -0,0 +1,147 @@
+// SPDX-FileCopyrightText: 2025-2026 Sergey Sharshunov <s.sharshunov@gmail.com>
+// SPDX-License-Identifier: LGPL-3.0-only
+
+#ifndef C166_COMMON_H
+#define C166_COMMON_H
+
+#include <rz_types.h>
+#include <rz_vector.h>
+#include <rz_analysis.h>
+#include <analysis_private.h>
+
+#define H_NIB(x) (((x) & 0xF0) >> 4) ///< High nibble
+#define L_NIB(x) ((x) & 0x0F) ///< Low nibble
+
+// Core Special Function Registers (CSFR)
+#define BASE_GPR_ADDR    0xFE10 ///< Base address for calculate GPR physical address (also REG_CP)
+#define BASE_SFR_ADDR    0xFE00 ///< Base address for calculate SFR physical address (also REG_DPP0)
+#define BASE_ESFR_ADDR   0xF000 ///< Base address for calculate ESFR physical address
+#define BASE_RAM_B_ADDR  0xFD00 ///< Base address for calculate RAM physical address (bit)
+#define BASE_SFR_B_ADDR  0xFF00 ///< Base address for calculate SFR physical address (bit)
+#define BASE_ESFR_B_ADDR 0xF100 ///< Base address for calculate ESFR physical address (bit)
+
+#define QX0   0xF000 ///< MAC Offset Register X0 (ESFRs)
+#define QX1   0xF002 ///< MAC Offset Register X1 (ESFRs)
+#define QR0   0xF004 ///< MAC Offset Register R0 (ESFRs)
+#define QR1   0xF006 ///< MAC Offset Register R1 (ESFRs)
+#define CPUID 0xF00C ///< CPU Identification Register (ESFRs)
+
+#define REG_PSW 0xFF10 ///< Processor Status Word
+
+#define REG_DPP0    (BASE_SFR_ADDR + 0x00) ///< CPU Data Page Pointer 0 Register (10 bits)
+#define REG_DPP1    (BASE_SFR_ADDR + 0x02) ///< CPU Data Page Pointer 1 Register (10 bits)
+#define REG_DPP2    (BASE_SFR_ADDR + 0x04) ///< CPU Data Page Pointer 2 Register (10 bits)
+#define REG_DPP3    (BASE_SFR_ADDR + 0x06) ///< CPU Data Page Pointer 3 Register (10 bits)
+#define REG_CSP     (BASE_SFR_ADDR + 0x08) ///< Code Segment Pointer
+#define REG_MDH     (BASE_SFR_ADDR + 0x0c) ///< Multiply Divide High Word
+#define REG_MDL     (BASE_SFR_ADDR + 0x0e) ///< Multiply Divide Low Word
+#define REG_CP      (BASE_SFR_ADDR + 0x10) ///< CPU Context Pointer Register
+#define REG_SP      (BASE_SFR_ADDR + 0x12) ///< Stack Pointer Register
+#define REG_STKOV   (BASE_SFR_ADDR + 0x14) ///< Stack Overflow Pointer
+#define REG_STKUN   (BASE_SFR_ADDR + 0x16) ///< Stack Underflow Pointer
+#define REG_CPUCON1 (BASE_SFR_ADDR + 0x18) ///< Core Control Register
+#define REG_CPUCON2 (BASE_SFR_ADDR + 0x1A) ///< Core Control Register
+#define REG_MAL     (BASE_SFR_ADDR + 0x5C) ///< MAC Accumulator – Low Word
+#define REG_MAH     (BASE_SFR_ADDR + 0x5E) ///< MAC Accumulator – High Word
+
+#define IDX0   0xFF08 ///< Address Pointer IDX0
+#define IDX1   0xFF0A ///< Address Pointer IDX1
+#define SPSEG  0xFF0C ///< Stack Pointer Segment Register
+#define MDC    0xFF0E ///< (Bit addressable) Multiply Divide Control Register
+#define PSW    0xFF10 ///< (Bit addressable) Program Status Word
+#define VECSEG 0xFF12 ///< (Bit addressable) Vector Table Segment Register
+#define ZEROS  0xFF1C ///< (Bit addressable) Constant Value 0s Register (read only)
+#define ONES   0xFF1E ///< (Bit addressable) Constant Value 1s Register (read only)
+#define TFR    0xFFAC ///< (Bit addressable) Trap Flag Register
+#define MRW    0xFFDA ///< (Bit addressable) MAC Repeat Word
+#define MCW    0xFFDC ///< (Bit addressable) MAC Control Word
+#define MSW    0xFFDE ///< (Bit addressable) MAC Status Word
+
+#define REG_ASC0_TIC 0xFF6C ///< Serial Channel 0 Transmit Interrupt Control Register
+#define REG_ASC0_RIC 0xFF6E ///< Serial Channel 0 Receive Interrupt Control Register
+
+/*!
+ * \brief C166 Branch Condition Codes
+ *
+ * Defines condition codes used for conditional branching instructions
+ * Datasheet page 39
+ * (*) Only usable with the JMPA and CALLA instructions
+ */
+// clang-format off
+typedef enum {
+	C166_CC_UC = 0x00,	///< CCNc = 0x00; [0D] Unconditional
+	C166_CC_NET = 0x02,	///< CCNc = 0x01; [1D] Not equal AND not end of table
+	// C166_CC_Z = 0x04,	///< CCNc = 0x02; [2D] Zero
+	C166_CC_EQ = 0x04,	///< CCNc = 0x02; [2D] Equal
+	// C166_CC_NZ = 0x06,	///< CCNc = 0x03; [3D] Not zero
+	C166_CC_NE = 0x06,	///< CCNc = 0x03; [3D] Not equal
+	C166_CC_V = 0x08,	///< CCNc = 0x04; [4D] Overflow
+	C166_CC_NV = 0x0A,	///< CCNc = 0x05; [5D] No overflow
+	C166_CC_N = 0x0C,	///< CCNc = 0x06; [6D] Negative
+	C166_CC_NN = 0x0E,	///< CCNc = 0x07; [7D] Not negative
+	C166_CC_C = 0x10,	///< CCNc = 0x08; [8D] Carry
+	// C166_CC_ULT = 0x10,	///< CCNc = 0x08; [8D] Unsigned less than
+	C166_CC_NC = 0x12,	///< CCNc = 0x09; [9D] No carry
+	// C166_CC_UGE = 0x12,	///< CCNc = 0x09; [9D] Unsigned greater than or equal
+	C166_CC_SGT = 0x14,	///< CCNc = 0x0A; [AD] Signed greater than
+	C166_CC_SLE = 0x16,	///< CCNc = 0x0B; [BD] Signed less than or equal
+	C166_CC_SLT = 0x18,	///< CCNc = 0x0C; [CD] Signed less than
+	C166_CC_SGE = 0x1A,	///< CCNc = 0x0D; [DD] Signed greater than or equal
+	C166_CC_UGT = 0x1C,	///< CCNc = 0x0E; [ED] Unsigned greater than
+	C166_CC_ULE = 0x1E,	///< CCNc = 0x0F; [FD] Unsigned less than or equal
+
+	C166_CC_NUSR0 = 0x01,     ///< USR-bit 0 is cleared (*)
+	C166_CC_NUSR1 = 0x03,     ///< USR-bit 1 is cleared (*)
+	C166_CC_USR0 = 0x05,      ///< USR-bit 0 is set 1
+	C166_CC_USR1 = 0x07       ///< USR-bit 1 is set 1
+} C166CondCode;
+
+typedef enum {
+	C166_EXT_MODE_NONE,
+	C166_EXT_MODE_ATOMIC,
+	C166_EXT_MODE_REG,
+	C166_EXT_MODE_PAGE,
+	C166_EXT_MODE_SEG,
+} C166ExtMode;
+
+// clang-format off
+typedef struct {
+	bool esfr;  		///< Extended register sequence active
+	C166ExtMode mode; 	///< Extended page/seq mode
+	ut8 i; 			///< Number of unstructions remaining until state exits
+	ut16 value; 		///< Value of ext
+} C166ExtState;
+
+typedef struct {
+	ut32 last_addr; 	///< State of last addr dissassembled
+	C166ExtState ext;
+	RzPVector /*<RzAsmTokenPattern *>*/ *token_patterns;
+	bool inited;
+} C166State;
+// clang-format on
+
+extern const char *const c166_rw[];
+extern const char *const c166_rb[];
+extern const char *const conds_names[];
+extern const char *const c166_extx_names[];
+
+const char *conds(ut8 cc);
+const char *conds_extended(ut8 cc);
+
+static inline bool IS_GPR(ut8 addr) {
+	return addr >= 0xF0 && addr <= 0xFF;
+}
+
+static inline bool IS_RAM(ut8 addr) {
+	return addr <= 0x7F;
+}
+
+static inline bool IS_rSFR(ut8 addr) {
+	return addr <= 0xEF;
+}
+
+static inline bool IS_bSFR(ut8 addr) {
+	return addr >= 0x80 && addr <= 0xEF;
+}
+
+#endif /* C166_COMMON_H */