SystolicFormer is a transformer attention accelerator prototype. It focuses on the fixed-point matrix kernels behind Q/K/V projection, QK^T score generation, masking, approximate softmax, and Attention*V context generation.
- Parameterizable SystemVerilog INT8 systolic-array building blocks.
- Tiled matrix execution model for projection, score, and context GEMMs.
- Register-driven accelerator control block with counters and error reporting.
- AXI-Lite shell for SoC integration.
- NumPy fixed-point reference model and descriptor-based runtime model.
- cocotb RTL tests, pytest reference tests, Verilator lint, and Yosys checks.
- AMD Kria KV260 platform contract for AXI-Lite control and DMA-buffer mapping.
The current SoC target is the AMD Kria KV260. The accelerator is exposed through an AXI-Lite control window, with tensor storage planned around a DDR-backed DMA buffer. The host check can exercise the register contract and counter behavior locally or through PYNQ MMIO on a board image.
Platform assumptions:
- Control window:
0xa0000000, 64 KiB, AXI-Lite, 32-bit registers. - DMA window:
0xa0010000, 64 KiB, AXI-DMA control. - Tensor buffer window:
0x10000000, 128 MiB, 64-byte aligned regions. - Clock target: 100 MHz.
- Array target: 8x8, with 16x16 as the sizing envelope.
python3 -m venv .venv
source .venv/bin/activate
python -m pip install -r requirements.txt
make env
make test-quick
make visualsUse make check for the full local regression and make synth for the Yosys
synthesis check.