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Releases: ryeleo/Mips-FPGA

lab_3: Merge pull request #18 from terminalstderr/readme

07 Jun 06:08

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Please see readme.md for a report/discussion. This work was performed by Ryan Leonard, Rui Tu, and Frank Arana.

At this release, we are able to run a MIPS implementation of fibbonacci using our IP.

Lab 2

30 May 01:07

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This work was performed by Rui Tu, Ryan Leonard, and Frank Arana.
This release contains a version of our MIPS CPU (mipscpu.v, mipscpu_tb.v).

Following instructions supported and tested:

  • addi
  • add
  • sw
  • lw

This includes the following modules:

  • control
  • alu control
  • decoder
  • rfwrite mux
  • rf
  • sign ext
  • alusrc mux
  • alu
  • data memory
  • wb mux