Electronics Engineering @ UPT · FPGA & RTL Design · Embedded Systems · Python
Bridging the gap between silicon and software. I design hardware from the gate level up and build the software systems that talk to it.
32-bit single-cycle CPU designed from scratch in SystemVerilog, deployed on Nexys A7-100T. Validated end-to-end with EEMBC CoreMark — 0.44 CoreMark/MHz, bit-exact CRC against published reference tables. Key challenge: 5-state FSM to synchronize a nominally single-cycle design with synchronous Block RAM.
SystemVerilog FPGA RISC-V Xilinx Vivado Bare-Metal C
Radix-2 Cooley-Tukey FFT implemented in VHDL with fixed-point arithmetic. Synthesis and timing analysis in Vivado, verified against MATLAB reference output.
VHDL FPGA DSP Fixed-Point Xilinx Vivado
Python system integrating with the MetaTrader 5 native COM/IPC bridge for real-time data acquisition and automated order execution. Engineering focus: floating-point broker compliance, stop-level validation, stateful execution control, process lifecycle management.
Python Streamlit MetaTrader5 API Windows IPC
Comparative analysis of classical Ziegler-Nichols PID tuning vs. Genetic Algorithm metaheuristic optimization for DC motor speed control, implemented in MATLAB/Simulink.
MATLAB Simulink Control Systems Genetic Algorithm
HDL SystemVerilog · VHDL · FPGA synthesis · timing analysis
Tools Xilinx Vivado · MATLAB/Simulink · Git
Embedded UART/SPI/I2C · bare-metal C · RISC-V Assembly
Languages C · C++ · Python
Web React · Tailwind CSS