Name		Name	Last commit message	Last commit date
EHD_FINAL_REPORT.pdf		EHD_FINAL_REPORT.pdf
PARALLEL_DIVISION_TB.v		PARALLEL_DIVISION_TB.v
README.md		README.md
Topmodule.v		Topmodule.v
adder_32.v		adder_32.v
comp_16.v		comp_16.v
comp_2.v		comp_2.v
comp_32.v		comp_32.v
comp_4.v		comp_4.v
comp_8.v		comp_8.v
division.v		division.v
fa.v		fa.v
finalsum.v		finalsum.v
ha.v		ha.v
paralleldiv.v		paralleldiv.v
rca.v		rca.v
readme.txt		readme.txt
sub4.v		sub4.v
subt.v		subt.v

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PAGERANK_ALGORITHM

Google Page rank Algorithm implemented using Verilog.

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Google Pagerank Algorithm implemented in Verilog

digital-design fpga parallelism pipelines verilog

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