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shreekanthkapparagaon/README.md

Shreekanth Kapparagaon Banner

Typing SVG


About

I'm an Electronics & Communication Engineer passionate about designing Digital Hardware, developing Embedded Systems, and building Engineering Software that bridges hardware and software.

My current goal is to build a high-quality open-source RTL IP library, engineering tools, and embedded projects while continuously expanding my expertise in Digital Design, Embedded Systems, and Engineering Software.


⚡ Engineering Focus

Building reliable hardware and the software that supports it.


⚡ Digital Design

Designing reusable RTL IPs using Verilog HDL.

Focus

RTL Design • FSM • Protocols • Verification

🔧 Embedded Systems

Developing firmware for modern embedded platforms.

Focus

ESP32 • STM32 • Arduino • Drivers

🐍 Engineering Software

Building tools that improve engineering productivity.

Focus

Python • Automation • CLI • GUI

🌐 Backend Development

Creating scalable backend applications and APIs.

Focus

Django • Flask • REST APIs • Databases

🚀 Featured Projects

A selection of projects that showcase my work in Digital Design, Embedded Systems, and Engineering Software.


🧩 VeriSketch

Verilog Visualization Tool

A Python-based tool for parsing Verilog HDL and generating architecture and RTL visualizations.

Tech Stack

Python Verilog CLI

View Repository →

📡 I²C Master Controller

Parameterized RTL IP

A synthesizable Verilog implementation of the I²C protocol with simulation and verification.

Tech Stack

Verilog FSM GTKWave

View Repository →

🚌 APB3 Slave Peripheral

AMBA APB3 Peripheral

A configurable APB3 slave featuring a register bank, complete verification, and documentation.

Tech Stack

Verilog AMBA APB3

View Repository →

📚 Smart LMS

Library Management System

A web-based library management system for managing books, members, borrowing, and returns.

Tech Stack

Python Django SQLite

View Repository →


🎯 Current Focus

Continuously improving my skills through hands-on projects and open-source development.


  • ⚡ Building a reusable RTL IP Library using Verilog HDL
  • 🧩 Developing VeriSketch, a Verilog visualization and analysis tool
  • 🔬 Exploring RTL Verification and SystemVerilog
  • 🔧 Expanding my Embedded Systems portfolio with ESP32 and STM32
  • 🐍 Creating Python tools that simplify engineering workflows

A quick overview of my GitHub activity and primary languages.

📊 GitHub Insights


Thanks for visiting!

Building Digital Hardware.
Embedded Systems.
Engineering Software.


Always learning. Always building.

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  1. verilog-spi-master-controller verilog-spi-master-controller Public

    FSM-based SPI Master Controller in Verilog HDL with FIFO buffering, configurable SPI modes, GTKWave verification, and GitHub Actions CI.

    Verilog

  2. parameterized-sync-fifo parameterized-sync-fifo Public

    Parameterized Synchronous FIFO in Verilog with extended pointer architecture, self-checking verification, and GitHub Actions CI.

    Verilog

  3. uart-verilog-transceiver uart-verilog-transceiver Public

    A modular UART (8N1) serial transceiver in Verilog featuring configurable baud rate, framing error detection, self-checking verification, waveform validation, and GitHub Actions CI.

    Verilog

  4. parameterized-apb3-slave parameterized-apb3-slave Public

    Parameterized AMBA APB3 Slave Peripheral in Verilog with configurable register bank, reusable APB Master BFM, and self-checking verification environment.

    Verilog

  5. BSMS BSMS Public

    Battery Sales Management System (BSMS) – A Python desktop application for managing inventory, sales, customers, and role-based access with real-world workflow design.

    Python

  6. embedx embedx Public

    Fast, modern CLI for embedded development — build, upload, and manage projects with ease.

    Python