I am a Distinguished Systems Architect and Technical Leader with 25+ years of experience specialized in building and stabilizing complex, distributed platforms, high-speed interconnects, and large-scale automation frameworks.
Proven track record directing 130+ engineer multi-disciplinary divisions and delivering large-scale automated system-level verification and regression environments. Trusted technical authority for global Tier-1 clients including Keysight, Siemens, FirstData, Orange UK, and AMEX.
(Thanks to Anurag Hazra for the github stats api)
- No-HBM Virtual Ultra Ethernet Test: Designed an HBM-free, affordable Ultra Ethernet Transport (UET) test compliance framework utilizing FPGA arrays, deterministic PRBS payloads, state hashing, and vRDMA. [Maths Simulation on Github] [Medium]
- No-Touch No-GPU Real-Time AI for Legacy Infra: Proposed an AI framework executing sub-microsecond real-time anomaly detection. Employs a cache-coherent architecture using DPDK SmartNICs, CXL 3.1, Ultra Ethernet, and line-rate L2 MACsec control loops to bypass OS kernel bottlenecks with zero disruption to live traffic. [Maths Simulation on Github] [Medium]
- ALP (अल्प) – Adaptive Little Language Protocol: Devised a unified, AI-inherent symbolic communication framework ensuring robust intent delivery across highly restricted bandwidth and fragile channel conditions. [Simulation on Github] [Medium]
- NTN Sustainability Control: Developed an Edge AI and gRPC-based distributed control layer designed to activate Non-Terrestrial Networks (NTN) under sustained 6G Sustainability (environmental/network) stress. [Dockerized Proto on Github] [Medium]
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- Languages & Frameworks: Python, C++, C#, Java, Edge AI, gRPC, Docker
- Systems & Networking: PCIe Gen6, CXL 3.1, P4-DPDK, Ultra Ethernet, vRDMA
- DevOps & CI/CD: GitHub Actions, Jenkins, BitBucket
- Division Leadership: Directed 130+ engineers cross-functional, multi-disciplinary division (spanning HW, Mechanical, FPGA, SW, Embedded, QA, and DevOps) to deliver end-to-end system validation schedules for global Tier-1 clients.
- Automation Architecture: Designed webhook-enabled, commit-triggered parallel CI/CD pipelines for multi-branch software, driver, and FPGA builds, automating hardware-in-the-loop (DUT) regression testing and artifact deployment.
- Performance Optimization: Engineered non-standard optimization routines in C++, reducing critical system code execution times by 65%-70%.
- Infrastructure Engineering: Architected and provisioned an IP network test lab with market cost INR 1.8 Crores for under INR 12 Lakhs using creative sourcing and self-experimentations.