- Being able to run a GameBoy game
Additional goals
- Being able to play sounds
- Being to use Serial communication
DMG Supported
Memory Bank Controllers:
- No Controller
- MBC1
- MBC3
Tested on:
- Windows 11
- sdl2 (for rust bindings):
- Fedora:
- For eframe:
sudo dnf install gtk3-devel - For SDL2:
sudo dnf install SDL2-devel
- For eframe:
- Ubuntu:
- For SDL2:
sudo apt-get install libsdl2-dev
- For SDL2:
- Fedora:
- Gameboy uses little endian
Cycle refers to an actual clock cycle for a clock frequency of (4.194304 MHz) and M-Cycle refers to 4 cycles. source
M-Cycles are used pretty often since all the instruction cycles are divisible by 4. The current implementation uses cycle as the Gameboy CPU (LR35902) instruction set uses it.
Halt instruction will be implemented as follows:
- When HALT is called, the system clock will be stopped and only an interruption will allow the clock to restart
- If the IME is not set, the interrupt code will not be executed and the process will restart after the HALT
Sources:
- Chapter 4 page 95: register code for D should be 010 instead of 101 (which is the code for L)
- Chapter 4 page 109: RLCA example, resulting register A should be 0x0B (and not 0x0A)
- 0xE2 and 0xF2 should have a length of one instead of 2
- JP (HL) should be JP HL
- All SRA commands should compute the carry flag (instead of resetting it)
- BIT (HL) should take only 12 cycles