FA4 consumer Blackwell (sm_120) integration: forward + backward + dispatcher fixes

[thad0ctor]

Integrates three open upstream PRs adding FA4 forward support for consumer Blackwell (sm_120) and adds the dispatcher fixes required to make sm_120 forward AND backward actually run end-to-end. Also tunes the SM120 forward tile selection per shape from a subprocess-isolated sweep.

What's here

Upstream PRs cherry-picked

• [Cute,Fwd,Sm120] Fix three forward-pass correctness bugs (use_tma_O, smem-store atom, pack_gqa) Dao-AILab/flash-attention#2553 — three forward-correctness fixes for sm_120 (disable use_tma_O in SM80 base, universal smem-store atom for SM80 MMA layout, default pack_gqa=False on consumer Blackwell)
• Add SM120 TMA forward kernel with warp specialization Dao-AILab/flash-attention#2349 — SM120 TMA forward kernel with warp specialization + SMEM fallback
• Add SM80/SM120 block-sparse forward attention support Dao-AILab/flash-attention#2389 — SM80/SM120 block-sparse forward attention support + get_total_block_count utility

What this PR adds on top of Dao-AILab#2553 + Dao-AILab#2349 + Dao-AILab#2389

The three upstream PRs are forward-only correctness/feature fixes. Even with all three merged, SM120 forward still doesn't work end-to-end (latent dispatcher and kernel bugs surface immediately) and backward hangs or asserts. This PR adds the integration glue + backward support + tile tuning + real paged-KV/pack_gqa that you don't get from cherry-picking the upstream PRs alone:

Capability	After Dao-AILab#2553 + Dao-AILab#2349 + Dao-AILab#2389 alone	After this PR
SM120 forward (dense d=64/128 MHA/GQA causal+non-causal)	crashes on first call (apply_score_mod arg-order bug, vec_size typo, is_split_kv kwarg, etc.)	works; max abs diff ~0.004 bf16
SM120 backward	crashes on first call (dQ_single_wg unbound, softmax_scale None→Float, atomic_add_fp32 signature mismatch)	works; max diff ~0.008 bf16, validated across d=64/96/128 × MHA/GQA × causal/non-causal × seqlen 32-4096 × batch 1-8
pack_gqa=True on SM120	crashes deep in CuTeDSL (crd2idx composite-mode collapse at pack_gqa.py:139)	works; produces bitwise-identical output to pack_gqa=False via flat-offset arithmetic in PackGQA.compute_ptr
qwen2.5-7b style (7-way GQA) on SM120	crashes in cute.local_tile ("failed to perform a valid division of ((7,?),?) by [128:1;128:1]")	works; auto-downgrades pack_gqa for GQA ratios that don't divide tile_m
Paged-KV on SM120 (any head_dim)	silently returns garbage (SM80-base accepts mPageTable kwarg but ignores it)	real implementation through head_dim=128; 38-case regression suite
Forward tile selection (per-shape lookup)	single tile per head_dim bracket (conservative: 128×128 for d≤64, 128×64 for d≤128)	per-shape lookup keyed on (head_dim, qhead_per_kvhead, seqlen, causal) tuned via subprocess-isolated sweep (60 cells × 5 candidates, top-3 reproducibility re-pass, strict ≥2% paired-validation acceptance, +num_stages override). Geomean 1.06× over the head_dim-only default, peak win +31% (hd64-small-gqa sl=2048 causal)
head_dim > head_dim_v (e.g. MLA absorbed)	hangs the GPU	routed to the non-TMA path which handles it correctly
d=256 forward	SMEM overflow crash	works with (64, 64, ns=1) tile bracket
varlen non-causal	cudaErrorIllegalAddress (out-of-bounds cu_seqlens read on over-launched grid tiles)	cu_seqlens index clamped; 36/36 varlen tests pass
Backward dQ postprocess	silent rmem→smem scrambling on SM120 (SM80 MMA layout vs SM90 stmatrix mismatch)	universal smem-store atom; permanent regression test with white-box source-inspection guard
Block-sparse forward on SM120	crashes (BlockSparseTensors 8-field unpack into 4 names + downstream DSL ICE)	works; 624/624 tests pass in test_block_sparsity.py
softcap / learnable_sink / score_mod forward	AttributeError on vec_size (typo in Dao-AILab#2349's TMA forward)	works; ULP-accurate vs fp32 SDPA+tanh reference
Invalid head_dim error	cudaErrorMisalignedAddress from device	clean host-side AssertionError
TMA forward varlen routing	silently routes seqused-only callers to TMA (which doesn't support varlen)	uses outer-scope is_varlen that includes seqused_q/k
apply_score_mod arg order	crashes or silently uses seqlen as softmax_scale (positional bug in Dao-AILab#2349)	fixed; both pass as keyword

Cherry-picking Dao-AILab#2553/Dao-AILab#2349/Dao-AILab#2389 alone gives you SM120 forward kernels that compile but fail at first dispatch. This PR is what makes them actually usable end-to-end for training and inference.

Performance vs PyTorch SDPA (RTX 5090, sm_120, bf16, batch=1, forward, this PR's tuned tip)

Paired validation: tuned FA4 averaged over multiple bench runs vs the best of (cuDNN, Flash-2) SDPA backends, measured via a standard per-cell harness (5 warmup + 30 iters, torch.cuda.Event median timing).

Model preset	Hq / Hkv / D	Peak FA4 TFLOPS	Peak best-SDPA TFLOPS	FA4 sl=4096 c=0	best-SDPA sl=4096 c=0	FA4 sl=4096 c=1	best-SDPA sl=4096 c=1
llama3-8b	32 / 8 / 128 (GQA 4:1)	183	185	181	165	166	150
qwen2.5-7b	28 / 4 / 128 (GQA 7:1)	177	186	177	166	160	146
mistral-7b	32 / 8 / 128 (GQA 4:1)	184	184	180	161	165	147
hd64-small-h16	16 / 16 / 64 (MHA)	175	177	154	155	122	128
hd64-small-gqa	16 / 4 / 64 (GQA 4:1)	183	174	164	137	126	105

Aggregate across 60 cells (5 models × 6 seqlens × 2 causal):

• Geomean FA4 / best-of-(cuDNN, Flash-2): 1.119×
• Peak FA4: 184 TFLOPS; peak best-SDPA: 186 TFLOPS
• Wins (>5% faster than best SDPA): 33 / 60
• Ties (±5%): 17 / 60
• Losses (>5% slower): 10 / 60

Notable: the GQA causal/mid-seqlen band where 7B-class training and decode spend most of their time consistently shows FA4 +10-30% over best-SDPA. The cells where FA4 loses concentrate at sl=16384 head_dim=128 (cuDNN's long-seqlen path is well-tuned there). PyTorch 2.11's SDPA also has a documented kernel-selector pothole at sl=2048-4096 head_dim=128 causal+GQA where it drops to 12-50 TFLOPS; FA4 doesn't.

Dispatcher fixes for SM120

• Initialize dQ_single_wg in the SM120 backward setup (was missing → UnboundLocalError)
• Keep softmax_scale non-None for SM80/SM120 backward dK epilogue (inline log2 computation like SM90 does)
• atomic_add_fp32: adopt the new keyword-only atomicrmw signature in nvidia-cutlass-dsl >= 4.x
• Drop unsupported is_split_kv kwarg on the SM120 forward path
• Pass split_idx=0, num_splits=1, seqlen_info=seqlen at the SM80/SM120 get_total_block_count call site (arity mismatch fix)
• Rename vec_size → score_vec_size on the SM120 TMA forward (was a typo, unblocks softcap/learnable_sink/score_mod)
• Auto-downgrade pack_gqa=False on SM120 when qhead_per_kvhead doesn't divide tile_m=128 (qwen2.5-7b's 7-way GQA fail), and when paged-KV is enabled (path interaction)
• Route head_dim > head_dim_v to the SM120 non-TMA path: bisection showed the hang lives in FlashAttentionForwardSm120Tma, not in the SM80-base mainloop as previously diagnosed. The non-TMA can_implement now accepts d > dv; the TMA can_implement still rejects it, so the dispatcher routes those shapes to the SM80-base kernel which handles them correctly (verified bitwise-identical to SDPA on the minimum repro and within bf16 noise across larger shapes)
• Route SM120 through the shared _validate_head_dims helper (invalid head_dim was reaching the kernel and faulting with cudaErrorMisalignedAddress)
• Clamp the cu_seqlens[batch_idx+1] read in SeqlenInfoQK.create so SM80/SM120 over-launched varlen tiles don't fault on a non-resident page
• Document why deterministic backward can't be lifted on SM120 (the SM80 base kernel itself lacks the dQ_semaphore code path; it's a feature gap shared with SM80, not an SM120 SMEM limit)

SM120-specific kernel work

• Real paged-KV forward on the SM80-base kernel via PagedKVManager, supported through head_dim = 128 using a paged-specific (128, 128, ns=1) tile (validated for d in {64, 96, 128} against SDPA on reconstructed K/V; max abs diff ~0.004 bf16). head_dim > 128 rejected at dispatch.
• Real pack_gqa=True support: rewrite PackGQA.compute_ptr to compute the flat offset arithmetically (avoid the cuTeDSL crd2idx collapse on composite mode 0); call pack_gqa_layout in the SM80-base forward
• Backward postprocess: force the universal smem-store atom for SM80/SM120 dQ (same class of bug as the forward fix in [Cute,Fwd,Sm120] Fix three forward-pass correctness bugs (use_tma_O, smem-store atom, pack_gqa) Dao-AILab/flash-attention#2553)
• D > 128 tile bracket (64, 64) for SM120 that fits the 99 KB SMEM cap (was overflowing); wire FlashAttentionForwardSm120.can_implement as a dispatch safety net

Per-shape SM120 forward tile + num_stages lookup

The SM120 forward dispatch consults a tile + num_stages lookup keyed on (head_dim, qhead_per_kvhead, seqlen, causal). Shapes outside the lookup fall back to the head_dim-only brackets that match the pre-tuning defaults.

The lookup was built from a subprocess-isolated sweep: each (cell, candidate) pair runs in a fresh python process so the JIT compile cache cannot silently bias rankings across candidates. The top-3 candidates per cell get a reproducibility re-measurement; variance > 10% excludes the candidate. A candidate replaces baseline only when its mean TFLOPS beats the baseline tile by ≥ 2% on paired bench runs; otherwise the cell falls back to baseline.

Verified

E2E suite on RTX 5090, sm_120, bf16 — 34 / 34 pass through the public flash_attn.cute.flash_attn_func / flash_attn_varlen_func API, max abs diff vs PyTorch SDPA math backend (with KV repeat-interleave for GQA reference):

Group	Shapes	Worst max abs diff
7B-class LLM forward (llama3-8b, mistral-7b, qwen2.5-7b at sl=1024 / sl=4096, causal + non-causal)	12 cases	0.0083
7B-class LLM backward (same models at sl=1024, causal + non-causal)	6 cases	0.0488 (dv on causal; matches bf16 noise)
head_dim > head_dim_v (previously hung the GPU): (B, S, H, d, dv) ∈ {(1,64,1,128,64), (2,2048,4,128,64), (1,1024,8,128,64)}, causal + non-causal	6 cases	0.0068
pack_gqa=True vs pack_gqa=False on 4-way GQA (llama-style)	2 cases	0.000000 (bitwise identical)
7-way GQA (qwen2.5-7b shape) hitting the pack_gqa auto-downgrade	2 cases	0.0087
Paged-KV at head_dim=128 via flash_attn_varlen_func (page_size=64, permuted page table)	2 cases	0.0083
Varlen forward at sl bin = {128, 64, 256, 192} (Bug A regression check — used to hit cudaErrorIllegalAddress)	2 cases	finite, correct shape
head_dim=256 forward (new tile bracket)	2 cases	0.0077

Additional pytest coverage in tests/cute/:

• test_paged_kv_sm120.py: 38 cases pass (page_size in {16, 64, 256}, identity / permuted / shared page tables, GQA + MQA, head_dim ∈ {64, 96, 128}, plus expected-rejection for head_dim ∈ {192, 256} and a cross-feature paged + d > dv + varlen correctness case)
• test_flash_attn_sm120_dgtdv.py: 11 cases pass (head_dim > head_dim_v routing, with pytest-timeout(30) so a future TMA-gate widening that re-introduces the kernel hang fails as a timeout rather than wedging the GPU)
• test_flash_attn_bwd_sm120_postprocess.py: 10 cases pass (backward dQ postprocess; combines a numeric vs-fp32-SDPA comparison with a white-box source-inspection guard against re-introduction of the buggy literal pattern)
• test_block_sparsity.py: 624 of the ~4900 collected cases run as a representative slice on sm_120 (all 624 pass)

Tile lookup paired validation (RTX 5090, multiple baseline runs + multiple tuned runs averaged, same bench harness):

• 60-cell grid (5 model presets × 6 seqlens × 2 causal): 38 improved >2%, 16 tied, 0 lookup-deviation regressions
• Geomean tuned/baseline: 1.06×
• Peak FA4: 184.3 → 187.3 TFLOPS
• Top wins: hd64-small-gqa sl=2048 causal +31%, sl=4096 causal +21%; mid-seqlen causal d=128 GQA shapes (llama3 / mistral / qwen) consistently +13–15%

Performance vs FlashAttention 2 (RTX 5090, sm_120, bf16)

Head-to-head bench against flash_attn 2.8.3 (Dao-AILab official wheel) on the same RTX 5090, same torch 2.11.0 + cu130 build. Each cell run in a fresh subprocess (defeat JIT cache pollution), 3 untimed warmups + 10 timed CUDA-event iterations, median latency reported, Dao FLOPs convention (4*B*H_q*S*S*D non-causal, halved for causal, 2.5× for backward). Matrix: 5 model presets (llama3-8b, mistral-7b, qwen2.5-7b, llama2-7b, mixtral-8x7b) × sl ∈ {1024, 2048, 4096, 8192} × causal ∈ {False, True} × direction ∈ {fwd, bwd} = 160 paired cells, all returning status: ok.

Forward (40 paired cells):

Metric	FA2 2.8.3	FA4 (this PR)
Geomean TFLOPS	153.0	154.7
Peak TFLOPS	193.0	195.7
Geomean FA4 / FA2	—	1.01×
Cells where FA4 ≥ FA2	—	22 / 40

Largest forward wins: qwen2.5-7b sl=1024 causal 1.13×, mistral-7b sl=2048 1.10×, mixtral-8x7b sl=2048 1.08×. Largest forward regression: llama2-7b sl=8192 causal 0.91× (MHA tail).

Backward (40 paired cells, timing backward pass only):

Metric	FA2 2.8.3	FA4 (this PR)
Geomean TFLOPS	145.6	142.1
Peak TFLOPS	178.4	180.8
Geomean FA4 / FA2	—	1.017×
Cells where FA4 ≥ FA2	—	29 / 40

Backward is now at or above FA2 parity on geomean across the 40-cell matrix. MHA (llama2-7b) cells run 1.064× geomean (FA4 beats FA2 by 6.4%), GQA cells (qwen2.5-7b 7-way + llama3-8b/mistral-7b/mixtral-8x7b 4-way) at 1.005× geomean. Top wins: llama2-7b sl=1024 causal 1.159×, llama3-8b sl=1024 causal 1.143×, mistral-7b sl=8192 causal 1.129×. Largest remaining regression: qwen2.5-7b sl=1024 non-causal 0.803×.

Phase 17 backward optimization — three shipped levers (separate commits on top of the squash base, not coalesced):

1. cute: flip SM120 backward d<=64 default num_stages 2->1 — Phase 16c discovery + tightened paired-validation bench (n_measure=30, interleaved trials) confirmed ns=1 wins on 31/40 d=64 backward cells. ns=2 was inherited from the SM80-base default but the async pipeline overhead exceeds the latency-hiding benefit at small tile size on consumer Blackwell. Arch-gated to arch==120 + head_dim<=64. +5.6% geomean on the d=64 sub-sweep. (Note: the Phase 13 head-to-head matrix is all d=128 so this commit doesn't appear in the numbers above.)
2. cute: SM120 backward repartition 4 warps -> 8 warps per block — NCU profile attributed the original 0.93× gap to parallelism: FA4 ran 4 warps/SM vs FA2's 8 warps/SM, both clamped to 1 block by ~82 KB SMEM. This commit repartitions the SM120 backward kernel to 256-thread / 8-warp blocks at the SAME SMEM footprint. The non-trivial bug surfaced by a first attempt (num_threads=128→256 works on non-causal but breaks all causal shapes with dQ/dK/dV errors of 5-20 vs the 0.004 baseline) was traced to the R2P bitmask fast-path in flash_attn/cute/mask.py:r2p_bitmask_below + sm90_col_to_r2p_idx assuming the standard SM80/SM90 per-thread column pattern (col-pairs at stride 8). With AtomLayoutSdP = (4,2,1) the SM120 256-thread configuration has 2 N-warps and the per-thread cols interleave at stride 16, so the R2P bitmask kept cells beyond the causal boundary. Fix: new r2p_compatible=False marker on FlashAttentionBackwardSm120. Arch-gated to sm_120 only. NCU after on mistral-7b sl=4096 c=1 bwd: theoretical occupancy 8.33% → 16.67% (now matches FA2), compute throughput 80.12% → 87.55% (within 1pp of FA2's 88.57%).
3. cute: SM120 backward v4 atomic dQ/dK/dV via 4-contig per-thread gmem layout — Phase 16a NCU profile showed FA4 emitted 192 REDG.E.ADD.F32 per CTA vs FA2's 32 (the SM120 SASS uses per-element red.global.add.f32). After the 256-thread repartition, restructuring gmem_tiled_copy_dQaccum from val_layout=(1) to val_layout=(4) with a 128-bit copy atom gives each thread 4 contiguous fp32 in gdQaccum. The MMA m16n8k16 C-fragment is flat-compact in register storage, so retile() to val_layout=(4) doesn't reorder data — red.global.add.v4.f32 lands at the correct 4 gmem positions. Wired for the dQ atomic loop AND the GQA dK/dV epilogue. Arch-gated to sm_120. Bench shows +1.76× over the prior tip on the 20-cell focused subset.

The original Phase 13 message about the backward tile tuning being a "negative result at d=128" still holds for the per-shape tile lookup approach explored in Phase 14 (only (64,64,ns=1) fits at d=128 + SMEM cap). The bench harness from that work is preserved at benchmarks/sm120_bwd_tuning/. The real gains came from the three commits above — restructuring the kernel itself, not picking among tile permutations.

FA4-only shapes (no FA2 reference — FA2 doesn't support these):

Shape	causal	FA4 ms	FA4 TFLOPS
d=128, dv=64 (Bug-E shape, B=2, S=4096, H=32)	N	2.26	182.5
d=128, dv=64	Y	1.35	152.3
d=192, dv=128 (B=2, S=2048, H=32)	N	1.02	169.1
d=192, dv=128	Y	0.63	135.5
d=256, dv=128 (B=2, S=2048, H=32)	N	1.18	174.1
d=256, dv=128	Y	0.68	150.9
paged-KV head_dim=128, page_size=64 (B=4, S=2048, H=8, permuted)	N	0.66	104.1
paged-KV head_dim=128, page_size=64	Y	0.46	75.1

These cells previously hung the GPU (d > dv Bug E) or were not implemented (paged-KV beyond the FA3 path); this PR makes them functional on sm_120 with no FA2 equivalent.

Raw data: bench/results.jsonl, per-cell subprocess logs preserved for replay.

Not in scope

• Deterministic backward on SM120 — asserts off, root cause is the SM80 base kernel lacks the dQ_semaphore code path (shared gap with SM80; lifting it on SM120 alone is not a small change).
• Paged-KV at head_dim > 128 — SM120's 99 KB SMEM cap can't fit the tile_n >= 128 PagedKVManager requirement plus d > 128 (would need 144 KB at d=192, 192 KB at d=256). Use SM100 / SM90 for those shapes.

Behavior changes from upstream (silent argument downgrades)

These auto-downgrades happen with no warning emitted. They keep callers correct but may surprise users who explicitly opt into the downgraded feature:

• pack_gqa=True + page_table != None → pack_gqa silently set to False. Reason: paged-KV's num_head_kv accounting conflicts with the packed mQ layout. Affects all arches that go through the SM120/SM80-base path.
• pack_gqa=True + num_splits != 1 + non-varlen → pack_gqa silently set to False. Pre-existing upstream behavior, no change.
• pack_gqa=True on SM120 when qhead_per_kvhead does not divide tile_m=128 (e.g. qwen2.5-7b's 7-way GQA) → silently downgraded so the cute.local_tile division succeeds. SM120-only.

Test plan

Run on a sm_120 GPU (RTX 5090 / RTX PRO 6000 Blackwell). All test files in tests/cute/ gate themselves on torch.cuda.get_device_capability() == (12, 0) and skip cleanly on other arches. Invoke pytest from a directory other than the repo root so the namespace flash_attn package isn't shadowed by the local FA2 __init__.py.

• tests/cute/test_paged_kv_sm120.py — paged-KV correctness through head_dim = 128, multiple page sizes / patterns, GQA + MQA, expected rejection for d > 128, plus a cross-feature paged + d > dv + varlen case (38 cases)
• tests/cute/test_flash_attn_sm120_dgtdv.py — head_dim > head_dim_v non-TMA routing regression suite, with pytest-timeout(30) so a future TMA-gate widening fails as a timeout instead of wedging the GPU (11 cases)
• tests/cute/test_flash_attn_bwd_sm120_postprocess.py — backward dQ postprocess regression: numeric vs fp32-SDPA comparison + white-box source-inspection guard against re-introduction of the buggy literal pattern (10 cases)
• tests/cute/test_block_sparsity.py — representative slice (~624 of ~4900 collected cases run on sm_120; all 624 expected to pass)
• Optional smokes for quick sanity:
  • Forward: a single bf16 flash_attn_func call vs F.scaled_dot_product_attention with SDPBackend.MATH, max abs diff < 0.05
  • Backward: same shape with requires_grad=True, compare dq/dk/dv against SDPA reference, max abs diff < 0.05

cc @coderabbitai

Summary by CodeRabbit

• New Features
  • Block-sparse attention execution support
  • SM120 TMA-optimized forward kernel path
  • Paged-KV support and improved paged-KV handling
• Bug Fixes
  • Improved SM120 head-dimension and tiling validation
  • Corrected GQA packing behavior when using paged-KV
  • Fixed sequence-length bounds for over-launched tiles and adjusted dQ store selection for SM120/SM80
• Tests
  • Added SM120 backward/postprocess, paged-KV, and dgtdv regression suites

[coderabbitai]

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📝 Walkthrough

Walkthrough

Adds an SM120 TMA forward path, SM80 block‑sparse mainloop and per‑block compute, updates SM120/SM80 dispatch and epilogue/backward glue, fixes PackGQA pointer math and seqlen safety, updates atomic API usage, and adds SM120 regression tests for paged‑KV and backward postprocess.

Changes

Block-sparse mainloop for SM80/SM120

Layer / File(s)	Summary
Kernel wiring & signatures for block-sparse flash_attn/cute/flash_fwd.py	Import block-sparse and paged‑KV utilities, extend kernel/call signatures to accept mPageTable and blocksparse_tensors, condition K/V formation on mPageTable, and wire block‑sparse params into launches.
Block-sparse mainloop helper flash_attn/cute/block_sparse_utils.py	run_block_sparse_mainloop_sm80 remaps m_block into sparse indices, reads masked/full block metadata using a fixed non‑varlen layout, iterates masked blocks first (applying mask_mod and seqlen masking for the first masked block), then full blocks, and returns processed_any.
Block-sparse per-block compute flash_attn/cute/flash_fwd.py	mma_one_n_block_bs implements a single block‑sparse KV iteration: K/V loads, QK GEMM, optional score_mod/masking, online softmax, and PV GEMM accumulation used by the block‑sparse mainloop.

SM120 TMA forward kernel with warp specialization

Layer / File(s)	Summary
Module and SMEM layout atom flash_attn/cute/flash_fwd_sm120_tma.py	get_smem_layout_atom_tma computes a TMA‑compatible SMEM swizzle/layout atom for Q/K/V based on dtype and k_dim.
TMA class init and feasibility flash_attn/cute/flash_fwd_sm120_tma.py	FlashAttentionForwardSm120Tma.__init__ configures DMA/MMA warp sizing and SM80 MMA paths; can_implement enforces dtype/dimension constraints (including head_dim <= head_dim_v), divisibility, and conservative SMEM+mbarrier capacity checks.
SMEM, helpers, and runtime kernel flash_attn/cute/flash_fwd_sm120_tma.py	Defines aligned SharedStorage with mbarrier arrays, apply_score_mod, attribute setup, and __call__ which prepares TMA descriptors/transposes/fast‑divs, partitions Q/K/V via TMA, initializes pipelines, runs consumer MMA loops for QK→mask→softmax→PV, and uses a dedicated DMA producer warp for TMA transfers; finalizes via epilogue.

SM120 dispatch, interface, and forward-sm120 changes

Layer / File(s)	Summary
SM120 class and can_implement tweak flash_attn/cute/flash_fwd_sm120.py	FlashAttentionForwardSm120.__init__ forces self.arch = Arch.sm_80 for SM80‑style epilogue paths; can_implement documents asymmetric‑head acceptance for the SM80 fallthrough.
Interface: validation, pack_gqa, tile defaults, and dispatch flash_attn/cute/interface.py	Adds SM120 head‑dim validation, disables pack_gqa for paged‑KV and incompatible qhead packing on SM120, introduces SM120 tiling/stage lookup (sm120_num_stages), clamps SplitKV, fixes compile cache keys to include per‑shape sm120_num_stages/page_size where appropriate, and selects the TMA path when eligible, otherwise falls back to the SM80 base or raises for unsupported paged‑KV/head_dim combos.

SM80 forward kernel adjustments and paged‑KV notes

Layer / File(s)	Summary
Prologue, pack_gqa, tile args, and seqlen flash_attn/cute/flash_fwd.py	When pack_gqa is enabled, repacks mQ/mO (and mLSE), adjusts TileSchedulerArguments.num_block for packed rows, and updates static seqlen bounds (seqlen_q_static/seqlen_k_static) to account for packing and page‑table extent.
Kernel signature and K/V pointer formation flash_attn/cute/flash_fwd.py	Kernel signature extended to accept mPageTable and blocksparse_tensors; contiguous gK/gV tile views and copy partitions are created only when mPageTable is None, otherwise K/V loads route through PagedKVManager.
Epilogue SMEM store atom enforcement flash_attn/cute/flash_fwd.py	Selects an SM80‑compatible SMEM store‑copy atom for the rmem→smem epilogue copy to keep copy behavior stable across SM80/SM120 variants.

SM80/SM120 hardening, backward, and utilities

Layer / File(s)	Summary
Backward softmax_scale_log2 computation flash_attn/cute/flash_bwd.py	Computes softmax_scale_log2 inline: softmax_scale * LOG2_E when self.score_mod is None, else LOG2_E.
Backward postprocess SMEM store atom selection flash_attn/cute/flash_bwd_postprocess.py	Computes store_atom_arch and forces it to 80 when self.arch // 10 is in {8,12} before calling utils.get_smem_store_atom(..., transpose=self.dQ_swapAB) to preserve the SM80/SM120 universal‑copy selection while keeping SM90 behavior.
Atomic utility API update flash_attn/cute/utils.py	atomic_add_fp32 updated to use the newer nvvm.atomicrmw keyword-only signature (op=..., ptr=..., a=...) with result type inferred from the operand.

PackGQA and seqlen safety fixes

Layer / File(s)	Summary
PackGQA pointer and load/store fixes flash_attn/cute/pack_gqa.py	compute_ptr now computes flat element offset via tensor.stride[0][0]/tensor.stride[0][1] and documents composite‑mode requirements; load_Q/store_O now pass unsliced tensors to preserve stride assumptions.
Seqlen clamp for over-launch safety flash_attn/cute/seqlen_info.py	Clamp batch_idx+1 index when reading mCuSeqlens* to shape[0]-1 to avoid out‑of‑bounds reads on scheduler over‑launched wasted tiles.

SM120-focused regression tests

Layer / File(s)	Summary
SM120 backward postprocess tests tests/cute/test_flash_attn_bwd_sm120_postprocess.py	Adds SM120-only regression and white‑box guard tests validating dQ/dK/dV within bf16 noise vs SDPA reference and asserting correct get_smem_store_atom usage.
SM120 paged‑KV forward tests and d>dv checks tests/cute/test_paged_kv_sm120.py, tests/cute/test_flash_attn_sm120_dgtdv.py	Adds paged‑KV harness, SDPA reference, routing shim, parameterized cases for page sizes/patterns/causal/GQA, negative NotImplemented checks for unsupported head_dim values, and d>dv routing/SMEM constraint tests to prevent SM120 hang regressions.

🎯 4 (Complex) | ⏱️ ~60 minutes

"🐰 I hopped through kernels, masks, and lanes,
TMA threads hummed while epilogue refrains,
Sparse blocks first, then full blocks keep time,
Tests and safety checks — a careful rhyme,
Code and carrots aligned in perfect lines."

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Docstring Coverage	⚠️ Warning	Docstring coverage is 56.06% which is insufficient. The required threshold is 80.00%.	Write docstrings for the functions missing them to satisfy the coverage threshold.

✅ Passed checks (4 passed)

Check name	Status	Explanation
Title check	✅ Passed	The title accurately and specifically summarizes the main objective: integrating FlashAttention v4 support for consumer Blackwell (SM120 GPUs) with forward, backward, and dispatcher improvements.
Linked Issues check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Description Check	✅ Passed	Check skipped - CodeRabbit’s high-level summary is enabled.

_{✏️ Tip: You can configure your own custom pre-merge checks in the settings.}

✨ Finishing Touches

🧪 Generate unit tests (beta)

• Create PR with unit tests
• Commit unit tests in branch sm120-integrate

---

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[coderabbitai]

Actionable comments posted: 2

🧹 Nitpick comments (4)

flash_attn/cute/block_sparse_utils.py (1)

708-758: ⚡ Quick win

Varlen path not supported – direct 4D indexing duplicates helper logic.

run_block_sparse_mainloop_sm80 hard-codes the non-varlen 4D indexing pattern (lines 750-758) instead of using get_curr_blocksparse_tensors which handles both varlen (2D) and non-varlen (4D) layouts. Other consumers like consume_block_sparse_loads (line 403) properly delegate to the helper.

If varlen + block-sparse on SM80/SM120 is intended to be supported later, the function should accept seqlen_info and use the existing helper. If not supported, consider adding a compile-time assertion.

♻️ Suggested refactor to use helper

 `@cute.jit`
 def run_block_sparse_mainloop_sm80(
     blocksparse_tensors: BlockSparseTensors,
     batch_idx,
     head_idx,
     m_block,
     mma_one_n_block,
     mask_fn,
     mask_mod,
     fastdiv_mods,
+    seqlen_info: SeqlenInfoQK,
     qhead_per_kvhead: cutlass.Constexpr[int] = 1,
     q_subtile_factor: cutlass.Constexpr[int] = 1,
 ):
     ...
-    mask_block_cnt, mask_block_idx, full_block_cnt, full_block_idx, *_ = blocksparse_tensors
-
     m_block_sparse = sparse_tensor_m_block(m_block, qhead_per_kvhead, q_subtile_factor)
-
-    curr_mask_block_cnt = mask_block_cnt[batch_idx, head_idx, m_block_sparse]
-    curr_mask_block_idx = mask_block_idx[batch_idx, head_idx, m_block_sparse, None]
-
-    if const_expr(full_block_cnt is not None):
-        curr_full_block_cnt = full_block_cnt[batch_idx, head_idx, m_block_sparse]
-        curr_full_block_idx = full_block_idx[batch_idx, head_idx, m_block_sparse, None]
-    else:
-        curr_full_block_cnt = Int32(0)
-        curr_full_block_idx = None
+    (
+        curr_mask_block_cnt,
+        curr_mask_block_idx,
+        curr_full_block_cnt,
+        curr_full_block_idx,
+    ) = get_curr_blocksparse_tensors(
+        batch_idx, head_idx, m_block_sparse, blocksparse_tensors, seqlen_info
+    )

🤖 Prompt for AI Agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flash_attn/cute/block_sparse_utils.py` around lines 708 - 758,
run_block_sparse_mainloop_sm80 duplicates non-varlen 4D indexing for mask/full
block tensors instead of using the shared helper; either update
run_block_sparse_mainloop_sm80 to accept seqlen_info and call
get_curr_blocksparse_tensors(...) (the same helper used by
consume_block_sparse_loads) so it correctly handles both varlen (2D) and
non-varlen (4D) layouts, or add a compile-time assertion in
run_block_sparse_mainloop_sm80 that varlen layouts are not supported; locate the
logic around curr_mask_block_cnt/curr_mask_block_idx and
curr_full_block_cnt/curr_full_block_idx and replace it with the helper call (or
assert) accordingly.

flash_attn/cute/flash_fwd_sm120_tma.py (3)

566-566: 💤 Low value

Remove unused variable n_block.

This variable is computed but never used in the kernel. The loop at line 784 computes cur_n_block = n_block_max - n_tile - 1 directly.

🧹 Suggested cleanup

         n_block_min, n_block_max = block_info.get_n_block_min_max(
             seqlen, m_block, split_idx, num_splits
         )
-        n_block = cutlass.max(n_block_max - 1, 0)

🤖 Prompt for AI Agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flash_attn/cute/flash_fwd_sm120_tma.py` at line 566, Remove the unused local
variable n_block (the expression n_block = cutlass.max(n_block_max - 1, 0))
since it is never referenced later; update the surrounding code to rely on the
existing computation cur_n_block = n_block_max - n_tile - 1 (and any uses of
n_block) so only n_block_max, n_tile, and cur_n_block remain; ensure no other
code paths reference n_block before deleting the assignment and related
dead-code.

---

23-44: 💤 Low value

Remove unused imports.

Several imports are flagged by static analysis as unused:

• Constexpr (line 23) — used as cutlass.Constexpr instead of the bare name
• PackGQA (line 37)
• NamedBarrierFwd (line 38)
• FastDivmodDivisor (line 44)

🧹 Suggested cleanup

-from cutlass import Constexpr, Float32, Int32, const_expr
+from cutlass import Float32, Int32, const_expr

-from flash_attn.cute.pack_gqa import PackGQA
-from flash_attn.cute.named_barrier import NamedBarrierFwd

-from cutlass.cute import FastDivmodDivisor

🤖 Prompt for AI Agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flash_attn/cute/flash_fwd_sm120_tma.py` around lines 23 - 44, Remove the
unused imports to clean up the module: delete the bare imports Constexpr,
PackGQA, NamedBarrierFwd, and FastDivmodDivisor from the top import block;
ensure code that currently refers to cutlass.Constexpr continues to use the
qualified name (cutlass.Constexpr) instead of the removed bare Constexpr, and
verify there are no references to PackGQA, NamedBarrierFwd, or FastDivmodDivisor
elsewhere in this file (e.g., search for PackGQA, NamedBarrierFwd,
FastDivmodDivisor) before removing them to avoid breaking references.

---

914-1003: 💤 Low value

mma_one_n_block method is unused.

This method is defined but never called. The kernel at lines 784–837 has the same logic inlined directly, with a comment at lines 780–783 explaining this is intentional to avoid CuTe DSL compiler hangs when pipeline states flow through method boundaries.

If this is dead code from development, consider removing it to reduce maintenance burden. If it's intended for future use, consider adding a comment indicating that.

🤖 Prompt for AI Agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flash_attn/cute/flash_fwd_sm120_tma.py` around lines 914 - 1003, The method
mma_one_n_block is defined but never used (its logic is inlined inside the
kernel to avoid CuTe DSL compiler hangs); either remove this dead function to
reduce maintenance or keep it but add a clear comment above mma_one_n_block
stating it is intentionally unused and kept for reference/future use (mention
the kernel that inlines the logic and the compiler-hang rationale), so future
readers know why it remains in the codebase.

🤖 Prompt for all review comments with AI agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Inline comments:
In `@flash_attn/cute/flash_fwd.py`:
- Around line 1384-1396: The call to apply_score_mod is passing seqlen as the
positional argument where softmax_scale belongs, causing an argument-order bug;
update the call in the const_expr(score_mod is not None) branch to pass
softmax_scale and seqlen by keyword (e.g., softmax_scale=softmax.softmax_scale,
seqlen=seqlen) or otherwise ensure softmax_scale is the 7th positional and
seqlen the 8th; reference the apply_score_mod invocation that currently uses
mma_params.thr_mma_qk, batch_idx, head_idx, m_block, acc_S, n_block, seqlen,
softmax_scale=... and mirror the correct ordering used in compute_one_n_block.

In `@flash_attn/cute/interface.py`:
- Around line 954-960: The local reassignment of is_varlen near the TMA kernel
selection overrides the earlier definition that includes seqused_q/seqused_k;
remove the redefinition (the lines that set is_varlen = cu_seqlens_q is not None
or cu_seqlens_k is not None) and use the previously computed is_varlen when
evaluating use_tma_sm120 (alongside page_table and use_block_sparsity) so
callers providing seqused_q/seqused_k are correctly treated as varlen.

---

Nitpick comments:
In `@flash_attn/cute/block_sparse_utils.py`:
- Around line 708-758: run_block_sparse_mainloop_sm80 duplicates non-varlen 4D
indexing for mask/full block tensors instead of using the shared helper; either
update run_block_sparse_mainloop_sm80 to accept seqlen_info and call
get_curr_blocksparse_tensors(...) (the same helper used by
consume_block_sparse_loads) so it correctly handles both varlen (2D) and
non-varlen (4D) layouts, or add a compile-time assertion in
run_block_sparse_mainloop_sm80 that varlen layouts are not supported; locate the
logic around curr_mask_block_cnt/curr_mask_block_idx and
curr_full_block_cnt/curr_full_block_idx and replace it with the helper call (or
assert) accordingly.

In `@flash_attn/cute/flash_fwd_sm120_tma.py`:
- Line 566: Remove the unused local variable n_block (the expression n_block =
cutlass.max(n_block_max - 1, 0)) since it is never referenced later; update the
surrounding code to rely on the existing computation cur_n_block = n_block_max -
n_tile - 1 (and any uses of n_block) so only n_block_max, n_tile, and
cur_n_block remain; ensure no other code paths reference n_block before deleting
the assignment and related dead-code.
- Around line 23-44: Remove the unused imports to clean up the module: delete
the bare imports Constexpr, PackGQA, NamedBarrierFwd, and FastDivmodDivisor from
the top import block; ensure code that currently refers to cutlass.Constexpr
continues to use the qualified name (cutlass.Constexpr) instead of the removed
bare Constexpr, and verify there are no references to PackGQA, NamedBarrierFwd,
or FastDivmodDivisor elsewhere in this file (e.g., search for PackGQA,
NamedBarrierFwd, FastDivmodDivisor) before removing them to avoid breaking
references.
- Around line 914-1003: The method mma_one_n_block is defined but never used
(its logic is inlined inside the kernel to avoid CuTe DSL compiler hangs);
either remove this dead function to reduce maintenance or keep it but add a
clear comment above mma_one_n_block stating it is intentionally unused and kept
for reference/future use (mention the kernel that inlines the logic and the
compiler-hang rationale), so future readers know why it remains in the codebase.

🪄 Autofix (Beta)

Fix all unresolved CodeRabbit comments on this PR:

• Push a commit to this branch (recommended)
• Create a new PR with the fixes

---

ℹ️ Review info

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Configuration used: defaults

Review profile: CHILL

Plan: Pro

Run ID: 9c771396-cc50-48ee-b2a8-55805d806e5e

📥 Commits

Reviewing files that changed from the base of the PR and between fe5fb1b and 2be4b7b.

📒 Files selected for processing (7)

• flash_attn/cute/block_sparse_utils.py
• flash_attn/cute/flash_bwd.py
• flash_attn/cute/flash_fwd.py
• flash_attn/cute/flash_fwd_sm120.py
• flash_attn/cute/flash_fwd_sm120_tma.py
• flash_attn/cute/interface.py
• flash_attn/cute/utils.py

[coderabbitai]

Actionable comments posted: 2

🤖 Prompt for all review comments with AI agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Inline comments:
In `@tests/cute/test_flash_attn_bwd_sm120_postprocess.py`:
- Around line 71-73: The inline continuation comment for the variable S in the
test (around the assignment "S = 1024") is misaligned and triggers Flake8
E114/E116; update the comment so its indentation matches the wrapped statement's
indentation (align the comment with the start of the "S = 1024" line or the
wrapped continuation indent) to satisfy linting rules, touching the
test_flash_attn_bwd_sm120_postprocess.py section containing S = 1024 and the
following comment.

In `@tests/cute/test_paged_kv_sm120.py`:
- Around line 36-38: Remove the unused imports causing Flake8 F401 in
tests/cute/test_paged_kv_sm120.py by deleting the import lines for math and os
(leave the necessary import for sys if used elsewhere); ensure only required
modules are imported so the top-of-file import block no longer includes math or
os.

🪄 Autofix (Beta)

Fix all unresolved CodeRabbit comments on this PR:

• Push a commit to this branch (recommended)
• Create a new PR with the fixes

---

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⚙️ Run configuration

Configuration used: defaults

Review profile: CHILL

Plan: Pro

Run ID: b8475edd-852f-436c-8947-c425cf37be30

📥 Commits

Reviewing files that changed from the base of the PR and between 2be4b7b and c402d74.

📒 Files selected for processing (10)

• flash_attn/cute/block_sparse_utils.py
• flash_attn/cute/flash_bwd_postprocess.py
• flash_attn/cute/flash_fwd.py
• flash_attn/cute/flash_fwd_sm120.py
• flash_attn/cute/flash_fwd_sm120_tma.py
• flash_attn/cute/interface.py
• flash_attn/cute/pack_gqa.py
• flash_attn/cute/seqlen_info.py
• tests/cute/test_flash_attn_bwd_sm120_postprocess.py
• tests/cute/test_paged_kv_sm120.py

[coderabbitai]

Caution

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⚠️ Outside diff range comments (1)

flash_attn/cute/interface.py (1)

1105-1105: ⚠️ Potential issue | 🟠 Major | ⚡ Quick win

Phase 5c tuned num_stages values are never applied to SM120 kernels.

The sm120_num_stages variable is computed at line 585 from the _SM120_TILE_LOOKUP (e.g., (64, 1, 2048, 1): (64, 64, 2) sets num_stages=2), but line 1105 hardcodes num_stages=1 instead of using the tuned value.

This means the Phase 5c performance tuning for SM120 is ineffective.

🐛 Proposed fix

                 fa_fwd = FlashAttentionForwardSm120(
                     dtype,
                     head_dim,
                     head_dim_v,
                     qhead_per_kvhead,
                     is_causal=causal,
                     is_local=local,
                     pack_gqa=pack_gqa,
                     tile_m=tile_m,
                     tile_n=tile_n,
-                    num_stages=1,
+                    num_stages=sm120_num_stages,
                     num_threads=num_threads,
                     Q_in_regs=False,
                     score_mod=score_mod,
                     mask_mod=mask_mod,
                     has_aux_tensors=aux_tensors is not None,
                 )

🤖 Prompt for AI Agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flash_attn/cute/interface.py` at line 1105, The code hardcodes num_stages=1
where SM120 kernels should use the tuned sm120_num_stages computed from
_SM120_TILE_LOOKUP; update the call/site that currently passes num_stages=1 to
instead pass the variable sm120_num_stages (the value computed at line ~585) so
Phase 5c SM120 tuning is applied, ensuring any downstream uses (function/class
where num_stages is supplied) accept and propagate that variable rather than the
literal 1.

🧹 Nitpick comments (1)

flash_attn/cute/interface.py (1)

899-901: 💤 Low value

Comment is misleading — Phase 5c lookup does not run for SM80.

The comment claims num_stages is set by "Phase 5c per-shape lookup," but the _SM120_TILE_LOOKUP logic (lines 535–592) is guarded by if arch // 10 == 12:, so it never executes for SM80. For SM80, sm120_num_stages stays at the default value of 1.

Consider updating the comment to reflect the actual behavior:

-                # num_stages set by Phase 5c per-shape lookup above (defaults
-                # to 1; bumped to 2 for shapes where K/V pipelining wins).
+                # SM80 uses 1 stage; SM120 overrides this in its own branch.
                 num_stages=sm120_num_stages,

🤖 Prompt for AI Agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flash_attn/cute/interface.py` around lines 899 - 901, The comment is
misleading about Phase 5c affecting num_stages; update the comment near the
num_stages=num_stages=sm120_num_stages assignment to say that the Phase 5c
per-shape lookup (_SM120_TILE_LOOKUP) runs only when arch // 10 == 12 (SM120),
so for SM80 sm120_num_stages remains the default 1; mention that num_stages is
therefore conditionally adjusted only for SM120 and defaults to 1 on SM80 to
avoid confusion.

🤖 Prompt for all review comments with AI agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Outside diff comments:
In `@flash_attn/cute/interface.py`:
- Line 1105: The code hardcodes num_stages=1 where SM120 kernels should use the
tuned sm120_num_stages computed from _SM120_TILE_LOOKUP; update the call/site
that currently passes num_stages=1 to instead pass the variable sm120_num_stages
(the value computed at line ~585) so Phase 5c SM120 tuning is applied, ensuring
any downstream uses (function/class where num_stages is supplied) accept and
propagate that variable rather than the literal 1.

---

Nitpick comments:
In `@flash_attn/cute/interface.py`:
- Around line 899-901: The comment is misleading about Phase 5c affecting
num_stages; update the comment near the num_stages=num_stages=sm120_num_stages
assignment to say that the Phase 5c per-shape lookup (_SM120_TILE_LOOKUP) runs
only when arch // 10 == 12 (SM120), so for SM80 sm120_num_stages remains the
default 1; mention that num_stages is therefore conditionally adjusted only for
SM120 and defaults to 1 on SM80 to avoid confusion.

---

ℹ️ Review info

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Configuration used: defaults

Review profile: CHILL

Plan: Pro

Run ID: a5f532f7-b808-4704-ac78-59bf83310c26

📥 Commits

Reviewing files that changed from the base of the PR and between c402d74 and c8a1864.

📒 Files selected for processing (3)

• flash_attn/cute/interface.py
• tests/cute/test_flash_attn_bwd_sm120_postprocess.py
• tests/cute/test_paged_kv_sm120.py

💤 Files with no reviewable changes (1)

• tests/cute/test_paged_kv_sm120.py

[coderabbitai]

Actionable comments posted: 1

🤖 Prompt for all review comments with AI agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Inline comments:
In `@flash_attn/cute/interface.py`:
- Around line 1104-1107: The forward JIT cache key (compile_key) currently omits
sm120_num_stages while the SM120 kernel selection uses it
(num_stages=sm120_num_stages), leading to cache collisions across shapes; update
the compile_key construction (the same place that builds the forward compile
cache key) to include sm120_num_stages so that compile_key distinguishes
variants by num_stages and prevents reusing a compiled kernel with the wrong
sm120_num_stages.

🪄 Autofix (Beta)

Fix all unresolved CodeRabbit comments on this PR:

• Push a commit to this branch (recommended)
• Create a new PR with the fixes

---

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Configuration used: defaults

Review profile: CHILL

Plan: Pro

Run ID: 8d4bc294-813d-427f-b7d8-eb453f985493

📥 Commits

Reviewing files that changed from the base of the PR and between c8a1864 and be9e112.

📒 Files selected for processing (1)

• flash_attn/cute/interface.py

[coderabbitai]

Caution

Some comments are outside the diff and can’t be posted inline due to platform limitations.

⚠️ Outside diff range comments (1)

flash_attn/cute/interface.py (1)

1028-1042: ⚠️ Potential issue | 🟠 Major | ⚡ Quick win

can_implement check uses hardcoded num_stages=1 instead of sm120_num_stages.

The can_implement call at line 1033 passes num_stages=1, but the kernel is instantiated at line 1053 with num_stages=sm120_num_stages. Since sm120_num_stages can be 2 from the Phase 5c lookup table (e.g., (64, 1, 2048, 1): (64, 64, 2)), the SMEM check validates for 1-stage but the kernel runs with 2 stages — potentially overflowing the 99 KB SMEM cap.

🐛 Proposed fix

                 assert FlashAttentionForwardSm120.can_implement(
                     dtype, head_dim, head_dim_v, tile_m, tile_n,
-                    num_stages=1, num_threads=num_threads, is_causal=causal,
+                    num_stages=sm120_num_stages, num_threads=num_threads, is_causal=causal,
                     Q_in_regs=False,
                 ), (

🤖 Prompt for AI Agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flash_attn/cute/interface.py` around lines 1028 - 1042, The SM 12.0
validation wrongly hardcodes num_stages=1 when calling
FlashAttentionForwardSm120.can_implement, which can mis-validate SMEM usage vs
the actual kernel instantiation using sm120_num_stages; update the can_implement
call to pass num_stages=sm120_num_stages (preserving the other parameters like
dtype, head_dim, head_dim_v, tile_m, tile_n, num_threads, is_causal, Q_in_regs)
so the SMEM/hang/divisibility checks reflect the real kernel configuration used
later when creating the FlashAttentionForwardSm120 kernel.

🧹 Nitpick comments (2)

flash_attn/cute/flash_fwd.py (1)

1700-1701: 💤 Low value

Dead variables: smem_pipe_read and smem_pipe_write are unused.

These variables are initialized but never read. Since num_stages == 1 is enforced by the assertion at line 1655, all SMEM accesses use hardcoded index 0 (e.g., sK[None, None, 0]). Consider removing them.

♻️ Proposed fix to remove dead variables

-        smem_pipe_read = Int32(0)
-        smem_pipe_write = Int32(0)
         nb = n_block

🤖 Prompt for AI Agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flash_attn/cute/flash_fwd.py` around lines 1700 - 1701, Remove the dead
variables smem_pipe_read and smem_pipe_write which are initialized but never
used; since the assertion enforcing num_stages == 1 (see assertion around
num_stages) makes all SMEM accesses use the fixed index 0 (e.g., sK[None, None,
0]), delete the Int32(0) declarations for smem_pipe_read and smem_pipe_write and
any related unused references so there is no unused state left in the
flash_fwd.py top-level scope.

flash_attn/cute/block_sparse_utils.py (1)

788-811: 💤 Low value

Consider explicitly passing mask_mod=None for full blocks for consistency.

In consume_block_sparse_loads (lines 470, 480), when transitioning from mask blocks to full blocks, mask_mod=None is explicitly passed. Here, mask_mod is omitted for full blocks, relying on a default value in apply_mask. While this likely works if apply_mask defaults mask_mod=None, explicit passing would be clearer and consistent with the SM90/SM100 consumer path.

♻️ Proposed fix for explicit mask_mod=None

     if const_expr(full_block_cnt is not None):
         if curr_full_block_cnt > 0:
             n_block = curr_full_block_idx[curr_full_block_cnt - 1]
             if curr_mask_block_cnt == 0:
                 mma_one_n_block(
                     n_block=n_block,
-                    mask_fn=partial(mask_fn, mask_seqlen=True),
+                    mask_fn=partial(mask_fn, mask_mod=None, mask_seqlen=True),
                     is_first_n_block=True,
                 )
             else:
                 mma_one_n_block(
                     n_block=n_block,
-                    mask_fn=partial(mask_fn, mask_seqlen=True),
+                    mask_fn=partial(mask_fn, mask_mod=None, mask_seqlen=True),
                     is_first_n_block=False,
                 )
             for j in cutlass.range(1, curr_full_block_cnt):
                 n_block = curr_full_block_idx[curr_full_block_cnt - 1 - j]
                 mma_one_n_block(
                     n_block=n_block,
-                    mask_fn=partial(mask_fn, mask_seqlen=False),
+                    mask_fn=partial(mask_fn, mask_mod=None, mask_seqlen=False),
                     is_first_n_block=False,
                 )

🤖 Prompt for AI Agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@flash_attn/cute/block_sparse_utils.py` around lines 788 - 811, The full-block
handling in the block-sparse consumer omits an explicit mask_mod, relying on
apply_mask's default; change the two mma_one_n_block calls in the full-block
section so they pass mask_mod=None (i.e., the first call with
mask_fn=partial(mask_fn, mask_seqlen=True), is_first_n_block=True/False should
also include mask_mod=None, and the subsequent calls using mask_seqlen=False
should likewise include mask_mod=None) to match the consume_block_sparse_loads
behavior and the SM90/SM100 path and make intent explicit.

🤖 Prompt for all review comments with AI agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Outside diff comments:
In `@flash_attn/cute/interface.py`:
- Around line 1028-1042: The SM 12.0 validation wrongly hardcodes num_stages=1
when calling FlashAttentionForwardSm120.can_implement, which can mis-validate
SMEM usage vs the actual kernel instantiation using sm120_num_stages; update the
can_implement call to pass num_stages=sm120_num_stages (preserving the other
parameters like dtype, head_dim, head_dim_v, tile_m, tile_n, num_threads,
is_causal, Q_in_regs) so the SMEM/hang/divisibility checks reflect the real
kernel configuration used later when creating the FlashAttentionForwardSm120
kernel.

---

Nitpick comments:
In `@flash_attn/cute/block_sparse_utils.py`:
- Around line 788-811: The full-block handling in the block-sparse consumer
omits an explicit mask_mod, relying on apply_mask's default; change the two
mma_one_n_block calls in the full-block section so they pass mask_mod=None
(i.e., the first call with mask_fn=partial(mask_fn, mask_seqlen=True),
is_first_n_block=True/False should also include mask_mod=None, and the
subsequent calls using mask_seqlen=False should likewise include mask_mod=None)
to match the consume_block_sparse_loads behavior and the SM90/SM100 path and
make intent explicit.

In `@flash_attn/cute/flash_fwd.py`:
- Around line 1700-1701: Remove the dead variables smem_pipe_read and
smem_pipe_write which are initialized but never used; since the assertion
enforcing num_stages == 1 (see assertion around num_stages) makes all SMEM
accesses use the fixed index 0 (e.g., sK[None, None, 0]), delete the Int32(0)
declarations for smem_pipe_read and smem_pipe_write and any related unused
references so there is no unused state left in the flash_fwd.py top-level scope.

---

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📒 Files selected for processing (9)

• flash_attn/cute/block_sparse_utils.py
• flash_attn/cute/flash_bwd_postprocess.py
• flash_attn/cute/flash_fwd.py
• flash_attn/cute/flash_fwd_sm120.py
• flash_attn/cute/flash_fwd_sm120_tma.py
• flash_attn/cute/interface.py
• flash_attn/cute/pack_gqa.py
• flash_attn/cute/seqlen_info.py
• flash_attn/cute/utils.py

[thad0ctor]

@coderabbitai review

Force-pushed: squashed all thad0ctor commits into one (cee3b54) on top of the 8 upstream cherry-picks (Dao-AILab#2553/Dao-AILab#2349/Dao-AILab#2389 — authors preserved). Fixes vs the prior review batch:

• CRITICAL SM90 forward epilogue regression (from upstream [Cute,Fwd,Sm120] Fix three forward-pass correctness bugs (use_tma_O, smem-store atom, pack_gqa) Dao-AILab/flash-attention#2553's bc67a9c) now arch-gated: SM80/SM120 force universal copy, SM90 keeps WGMMA-paired stmatrix
• Added tests/cute/test_flash_attn_sm120_dgtdv.py regression suite for the Bug E non-TMA routing (11 cases, pytest-timeout(30) so a future regression fails as timeout vs GPU wedge)
• FlashAttentionForwardSm120.can_implement assertion now uses sm120_num_stages (was hardcoded num_stages=1)
• Cross-feature: paged-KV + d > dv + varlen now verified correct (max abs diff ~0.002 vs SDPA on reconstructed K/V); the previously-stale rejection test is now a correctness check
• E2E suite on RTX 5090: 34/34 pass through the public API across 7B-class LLM shapes (fwd+bwd), Bug E d>dv, pack_gqa, qwen 7-way GQA, paged-KV d=128, varlen, d=256
• PR body claims tightened per skeptical review (Behavior Changes section added; d=256/d=96 coverage caveated; "624/4900" instead of "624/624")

Please do a full review on the squashed diff.

[coderabbitai]

@thad0ctor Thanks for the detailed summary of the squashed commit. I'll kick off a full review of the updated diff now, including the SM90 epilogue arch-gating fix, the new test_flash_attn_sm120_dgtdv.py regression suite, the can_implement assertion correction, and the paged-KV cross-feature improvements.

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Full review triggered.

[thad0ctor]

@coderabbitai full review

[coderabbitai]

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[thad0ctor]

Independent verification of squashed tip (cee3b54) — all green on RTX 5090 (sm_120)

Re-ran the full test plan from a worktree-isolated agent on a fresh branch off cee3b54 (no source edits, no rebuild — same editable install + worktree overlay shim that pins flash_attn.cute to the worktree). Confirms the squash did not lose anything and the test-count claims in the PR body are accurate:

Check	Expected	Actual	Time
Forward smoke (FA4 vs SDPA, bf16)	SMOKE_OK	SMOKE_OK, max abs diff 0.0039	—
Backward smoke (dq/dk/dv vs SDPA, bf16)	BWD_SMOKE_OK	BWD_SMOKE_OK, max abs diff 0.0078	—
tests/cute/test_paged_kv_sm120.py	38 / 38	38 / 38	85.2 s
tests/cute/test_flash_attn_sm120_dgtdv.py	11 / 11	11 / 11	11.6 s
tests/cute/test_flash_attn_bwd_sm120_postprocess.py	10 / 10	10 / 10	39.0 s
E2E suite (7B-class LLM fwd+bwd, Bug E shapes, pack_gqa, 7-way GQA, paged-KV d=128, varlen, d=256)	34 / 34	34 / 34	—

GPU pinned by UUID to the RTX 5090 (GPU-f423fa54-c41a-719d-89ca-e09ae9c1826a); torch 2.11.0 + cu130; cuTeDSL 4.5.1. No hangs, no SIGKILL fired; longest single pytest run was paged-KV at 85 s. The only warnings emitted are the benign make_fragment is deprecated DeprecationWarning from nvidia_cutlass_dsl and a torch 2.11 sdp_kernel() FutureWarning in the forward smoke — both pre-existing, not introduced by this PR.

[thad0ctor]

@coderabbitai full review

[coderabbitai]

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[thad0ctor]

FA4 (this PR) vs FA2 2.8.3 benchmark — RTX 5090, sm_120, bf16, 160 paired cells + 8 FA4-only cells

Head-to-head on the same RTX 5090, same torch 2.11.0+cu130. Fresh subprocess per cell, 3 warmup + 10 timed CUDA-event iterations, median latency, Dao FLOPs convention. All 168 cells returned status: ok (0 fa2_unsupported, 0 timeouts).

Forward (40 paired cells):

• Geomean speedup FA4/FA2: 1.01×
• FA4 peak: 195.7 TFLOPS | FA2 peak: 193.0 TFLOPS
• FA4 ≥ FA2 on 22 / 40 cells
• Largest wins: qwen2.5-7b sl=1024 c 1.13×, mistral-7b sl=2048 1.10×, mixtral-8x7b sl=2048 1.08×
• Largest regression: llama2-7b sl=8192 c 0.91× (MHA tail)

Backward (40 paired cells):

• Geomean speedup FA4/FA2: 0.93× — FA4 backward is generally slower
• Root cause: SM80-base backward mainloop, no per-shape tile tuning yet for bwd, atomic_add_fp32 dQ accumulation. Closing this gap is a follow-up; the dQ_semaphore deterministic path is SM90-only (called out in "Not in scope").
• Wins where they happen: mistral-7b sl=8192 c 1.05×, llama2-7b sl=1024 c 1.09×, qwen2.5-7b sl=2048 1.01-1.07×

FA4-only shapes (no FA2 reference):

Shape	TFLOPS (non-causal)	TFLOPS (causal)
d=128, dv=64 Bug-E	182.5	152.3
d=192, dv=128	169.1	135.5
d=256, dv=128	174.1	150.9
paged-KV d=128, page=64 permuted	104.1	75.1

These shapes either hung the GPU (d > dv) or had no working path on sm_120 in earlier upstream PRs — this PR makes them functional.

Full per-cell table now in the PR body under "Performance vs FlashAttention 2".

[coderabbitai]

Actionable comments posted: 2

🤖 Prompt for all review comments with AI agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Inline comments:
In `@tests/cute/test_flash_attn_bwd_sm120_postprocess.py`:
- Around line 151-156: The test's assertion in
tests/cute/test_flash_attn_bwd_sm120_postprocess.py is brittle because it checks
an exact multi-line string for "get_smem_store_atom(\n                       
self.arch,"; update the guard to use a regex that ignores whitespace (e.g., use
re.search with a pattern like r"get_smem_store_atom\s*\(\s*self\.arch\s*,") so
it fails if self.arch is still passed as the first positional argument but
survives formatting changes; locate the assertion referencing
flash_bwd_postprocess.FlashAttentionBackwardPostprocess and replace the string
containment check with a whitespace-agnostic regex match that ensures self.arch
is not the first positional parameter (consider also allowing store_atom_arch to
appear).

In `@tests/cute/test_paged_kv_sm120.py`:
- Around line 223-230: The tests use Python's built-in hash(page_table_pattern)
for seeding (in test_page_table_patterns and the other paged-case test that
calls _run_paged_case), which is randomized per process; replace that with a
deterministic hash function or mapping (e.g., compute a stable integer from
page_table_pattern using hashlib.sha256 or zlib.crc32 and then mask to 16 bits)
and pass that stable seed into _run_paged_case so runs are reproducible; update
both occurrences where seed=hash(page_table_pattern) & 0xFFFF to use the
deterministic conversion instead.

🪄 Autofix (Beta)

Fix all unresolved CodeRabbit comments on this PR:

• Push a commit to this branch (recommended)
• Create a new PR with the fixes

---

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📒 Files selected for processing (13)

• flash_attn/cute/block_sparse_utils.py
• flash_attn/cute/flash_bwd.py
• flash_attn/cute/flash_bwd_postprocess.py
• flash_attn/cute/flash_fwd.py
• flash_attn/cute/flash_fwd_sm120.py
• flash_attn/cute/flash_fwd_sm120_tma.py
• flash_attn/cute/interface.py
• flash_attn/cute/pack_gqa.py
• flash_attn/cute/seqlen_info.py
• flash_attn/cute/utils.py
• tests/cute/test_flash_attn_bwd_sm120_postprocess.py
• tests/cute/test_flash_attn_sm120_dgtdv.py
• tests/cute/test_paged_kv_sm120.py

[thad0ctor]

Update — four new commits on sm120-integrate since the squash:

sha	summary
e06bc15	test: regex-based whitespace-agnostic white-box guard in test_flash_attn_bwd_sm120_postprocess.py (addresses CR MAJOR)
4670859	test: deterministic PATTERN_SEEDS mapping instead of hash(page_table_pattern) in test_paged_kv_sm120.py (addresses CR MINOR)
a0dd865	bench: backward tile sweep harness for sm_120 (benchmarks/sm120_bwd_tuning/)
47aa883	bench: loosen sweep correctness tol to 0.1 abs (bench-only, with rationale in commit body)

Phase 14 backward tile sweep — negative result, by design:

A subprocess-isolated sweep across the same 5 model presets × 4 seqlens × {causal, non-causal} = 40 cells used by the Phase 13 FA4-vs-FA2 bench. Acceptance gate: 0 cells regress >2% AND geomean ≥ 1.02×.

Result	Value
Geomean tuned/baseline	1.0000×
Cells with a tile that beats baseline	0 / 40
Cells regressed >2%	0

Root cause (documented in benchmarks/sm120_bwd_tuning/README.md): at head_dim=128, the SM80-base backward kernel's AtomLayout=(4,4,4) forces tile dimensions to multiples of 64, and SM120's 99 KB SMEM cap permits exactly one viable tile config: (tile_m=64, tile_n=64, num_stages=1) — which is already the hardcoded default. Every other candidate either fails to compile (SMEM overflow) or fails the dK/dV correctness check (0.4-0.75 abs diff vs SDPA, well past the 0.1 bench threshold).

So no _SM120_BWD_TILE_LOOKUP ships — there's nothing to tune at d=128. The bench harness is preserved as future tooling (e.g. for a hypothetical d=64 or d=192 backward path, or if the SM80-base AtomLayout constraint is ever relaxed).

dQ atomic audit (W2): also negative. The existing docstrings already accurately frame the SM80-only atomic_add_fp32 gap. No Blackwell-specific atomic variant offers a clear win without sacrificing L2 locality the postprocess relies on. No source change ships.

Verified: phase11_e2e/e2e.py still 34/34 on sm120-integrate tip after all four cherry-picks. The 4 new commits are not squashed; per-commit attribution preserved.

PR body's "Performance vs FlashAttention 2" section updated with this negative finding.

[thad0ctor]

Phase 17 backward optimization landed — please re-review the 3 new kernel commits + 2 test-file commits since the squash base cee3b54.

Summary of changes since the last review:

sha	summary
e06bc15	test: regex whitespace-agnostic white-box guard (addresses prior CR MAJOR)
4670859	test: deterministic PATTERN_SEEDS mapping (addresses prior CR MINOR)
a0dd865	bench: backward tile sweep harness (out-of-runtime-path tooling)
47aa883	bench: tol loosening (bench-only, with rationale)
4d59090	cute: SM120 backward d<=64 default num_stages 2→1 (Phase 17C, +5.6% on d≤64 cells, arch-gated)
362a65a	cute: SM120 backward repartition 4→8 warps/block (Phase 17A, occupancy 8.33%→16.67%, R2P bitmask fix in mask.py)
55ab672	cute: SM120 backward v4 atomic dQ/dK/dV (Phase 17D-lite, val_layout 1→4 + red.global.add.v4.f32 inline PTX)

Result on 40-cell Phase 13 backward bench (RTX 5090, bf16): FA4 / FA2 = 1.017× geomean (was 0.93×). Cells where FA4 ≥ FA2: 29 / 40 (was 10/40). Peak FA4 TFLOPS: 180.8 (was 167.0). MHA cells now beat FA2 by 6.4%; GQA cells at par.

All changes arch-gated to sm_120 only — flash_bwd_sm90.py and flash_bwd_sm100.py are bit-identical to cee3b54 (verifiable via git diff cee3b54..HEAD -- flash_attn/cute/flash_bwd_sm90.py flash_attn/cute/flash_bwd_sm100.py).

E2E phase11_e2e/e2e.py: 34/34. sm120 pytest (test_paged_kv_sm120.py 38, test_flash_attn_sm120_dgtdv.py 11, test_flash_attn_bwd_sm120_postprocess.py 10): 59/59.

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---

@thad0ctor Thanks for the detailed update and benchmark results. Here's the full review of the 7 commits since cee3b54.

---

Test fixes (e06bc15, 4670859) ✅

Both prior-review items are cleanly addressed:

• e06bc15: re.search(r"get_smem_store_atom\(\s*self\.arch\s*,", src) is None is the right approach — whitespace-agnostic, correct regex, and the inverted sense (is None == asserting the bad pattern is absent) is appropriate.
• 4670859: PATTERN_SEEDS = {"identity": 101, "permuted": 202, "shared": 303} is deterministic. Both call sites (test_page_table_patterns and test_d_gt64_page_table_patterns) are updated. ✅

---

Bench harness (a0dd865, 47aa883) — MAJOR: monkey-patch needle broken

benchmarks/sm120_bwd_tuning/measure_one_bwd.py calls _install_sm120_bwd_override_hook() at module import time. That function searches for this needle in the source of _flash_attn_bwd:

needle = (
    "    if arch // 10 == 12:\n"
    "        # SM120: uses SM80 MMA with 99 KB SMEM, 128 threads (4 warps).\n"
    "        m_block_size = 64\n"
    "        n_block_size = 64\n"
    "        if head_dim <= 64:\n"          # <-- removed by 4d59090
    "            num_stages_Q = 2\n"        # <-- removed by 4d59090
    "            num_stages_dO = 2\n"       # <-- removed by 4d59090
    "        else:\n"                       # <-- removed by 4d59090
    "            num_stages_Q = 1\n"
    "            num_stages_dO = 1\n"
)

But commit 4d59090 (in the same PR) replaces that if head_dim <= 64 conditional with an unconditional num_stages_Q = 1. The needle will not match the current interface.py, so the harness raises RuntimeError: monkey-patch needle not found on every invocation. The README's quick-start example is broken as shipped.

The fix is straightforward — update the needle to match the post-4d59090 source:

needle = (
    "    if arch // 10 == 12:\n"
    "        # SM120: uses SM80 MMA with 99 KB SMEM, 128 threads (4 warps).\n"
    "        m_block_size = 64\n"
    "        n_block_size = 64\n"
    "        # num_stages=1 across all head_dim on consumer Blackwell.\n"
    ...
    "        num_stages_Q = 1\n"
    "        num_stages_dO = 1\n"
)

(This is bench-only tooling, so it doesn't affect correctness of the kernel, but the harness is currently non-functional against this codebase.)

---

Phase 17C: d<=64 num_stages flip (4d59090) ✅

interface.py SM120 backward branch:

# Before: if head_dim <= 64: num_stages_Q = 2 / else: num_stages_Q = 1
# After:  unconditional num_stages_Q = 1, num_stages_dO = 1

Well-motivated by the paired-validation sweep (geomean 1.056×, 0 regressions >2% on 19 d=64 cells). Comment explains the rationale. ✅

---

Phase 17A: 4→8 warp repartition + R2P fix (362a65a) ✅ with one note

flash_bwd_sm120.py — arch: int = 120 as a class-level annotation is fine; getattr(self, "arch", 80) in the base kernel correctly picks it up.

flash_bwd.py R2P gating — the logic is correct:

• num_threads=256, WARP_SIZE=32 → num_mma_warps_sdp=8
• SdP_swapAB=False, AtomLayoutMSdP=4 → n_warps_sdp_val = 8 // 4 = 2
• 2 != 1 → r2p_compatible = False → R2P path disabled ✅

mask.py — r2p_compatible: cutlass.Constexpr[bool] = True default preserves SM80/SM90/SM100 behavior. The three r2p = const_expr(not self.swap_AB and self.r2p_compatible) guards are correctly placed. ✅

interface.py postprocess thread count — new elif arch // 10 == 12: num_threads_post_dQ = num_threads; num_threads_post_dKV = num_threads ensures postprocess writer and reader agree on the num_threads=256 stride. Critical correctness fix, correctly placed. ✅

Minor note: the removed debug lines (bidx = 0 and two commented-out cute.print_tensor lines) are a clean-up. ✅

---

Phase 17D: v4 atomic dQ/dK/dV (55ab672) ✅ with one note

utils.py — atomic_add_fp32_v4:

• PTX: red.global.add.v4.f32 [$0], abcd with constraint "l,f,f,f,f" is correct.
• The .reg .v4 .f32 abcd declaration inside the asm body is valid PTX inline syntax.
• The loop in dQ_mma increments by 4 and calls with elem_pointer(tdQgdQaccum_atomic, i), so the base address for each call is always at a 4-element (16-byte) boundary, satisfying red.global.add.v4.f32's alignment requirement. ✅

Minor note: the docstring says "must be naturally aligned to 16 bytes" but does not explain why callers can rely on this. Consider adding a brief inline comment at the call site (e.g. # 16-byte aligned: loop strides by 4 elements, base guaranteed by torch allocator) for future maintainers.

flash_bwd.py dQ_mma v4 loop:

for i in cutlass.range(0, n_atomic, 4, unroll_full=True):
    utils.atomic_add_fp32_v4(acc_dQ_atomic[i], ...[i+3], utils.elem_pointer(tdQgdQaccum_atomic, i))

assert n_atomic % 4 == 0 before the loop is appropriate. The GQA dK/dV path aliases gmem_tiled_copy_dQaccum (V=4) and uses identical v4 loops — consistent. ✅

flash_bwd_postprocess.py — SM120 num_s2r_copy_elems=4 now matches the main kernel's V=4 write pattern. The existing else: num_s2r_copy_elems = 4 for non-SM80/SM120 arches (SM90/100) is unchanged in effect since they go through a different code path. ✅

---

Summary

Area	Status	Notes
e06bc15 test regex fix	✅	Correctly addresses prior CR MAJOR
4670859 PATTERN_SEEDS	✅	Correctly addresses prior CR MINOR
a0dd865/47aa883 bench harness	⚠️ MAJOR	needle mismatch vs 4d59090 → RuntimeError on import
4d59090 ns=1 flip	✅	Well-validated, clean
362a65a 8-warp + R2P fix	✅	R2P logic correct, mask.py change minimal
55ab672 v4 atomic	✅	PTX correct, alignment guaranteed structurally

The only blocking item before merging is the bench harness needle — since it's out-of-runtime-path it won't affect users, but if you plan to use or share the sweep tooling it needs the needle updated to match the current interface.py. All kernel-path changes look correct.

🐇 =^._.^= (solid set of changes overall)