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Digital IC Design course assignments in Verilog RTL implementations

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NCKU Digital IC Design Course Assignments

This repository contains 5 homework assignments focusing on RTL design, hardware optimization, and IC design flow.

Structure

  • HW1: Median Finder Implementation
  • HW2: LCD Controller
  • HW3: FFT Implementation
  • HW4: Atrous Convolution with Bus Interface System
  • HW5: Max Convex Hull

Each homework folder contains:

  • RTL design files
  • Documentary materials
  • Pre-Layout simulation results

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Digital IC Design course assignments in Verilog RTL implementations

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