The required course work is Project 2 itself: a 16x4 SRAM design, analysis, and written report for ESE 3700 - Spring 2026 (Circuit Design and Optimization) at the University of Pennsylvania, School of Engineering and Applied Science.
This GitHub repository is not the official assignment submission. It exists for documentation, and personal record-keeping: LaTeX source, figures, SPICE decks, Electric exports, validation evidence, and a CI-built PDF.
Course assignment (instructor handout): The Spring 2026 Project 2 specification—requirements, figure of merit, and what counts as the assigned work—is published by Penn Engineering for ESE 3700 here: Project 2 handout (PDF). That PDF is course material, not something I wrote and not what this repository is hosting; it is linked only so readers can see the official brief. This repo is my own implementation, simulations, and write-up for that assignment.
Author: Tyrone Marhguy (contact links at the end of this page).
Figure 1 — Required vs. delivered headline metrics (from the LaTeX report).
ESE 3700, Spring 2026 - Project 2: 64 b SRAM in PTM 22 nm HP CMOS.
This repository documents a 64 b SRAM macro organized as 16 words x 4 bits in the PTM 22 nm High-Performance CMOS process at VDD = 1.0 V. The design is optimized around the project figure of merit:
FOM = 60 * BitcellArea * Power * Delay^2
Because delay is squared, the final architecture spends complexity in the periphery while keeping the repeated bitcell compact. The memory uses a standard 6T cell with asymmetric sizing (CR = 2, PR = 1), no column multiplexer, four parallel column slices, a clocked StrongARM sense amplifier, self-timed sense-amp enable from a replica bitline column, and a two-phase non-overlapping clocking scheme generated from the single external CLK.
Full detail: ESE3700_Proj2_Marhguy.pdf is generated by CI after a successful LaTeX build on main. The source of truth is ESE3700_Proj2_Marhguy.tex.
| Item | Implemented design |
|---|---|
| Memory organization | 16 rows x 4 columns; 64 b total |
| Process | PTM 22 nm High-Performance CMOS |
| Supply | VDD = 1.0 V |
| Interface | A[3:0], Din[3:0], Dout[3:0], WE, single CLK |
| Bitcell | 6T SRAM cell, CR = 2, PR = 1 |
| Bitcell area metric | 8 Wmin summed transistor width |
| Read architecture | Precharge/equalize + bitline discharge + StrongARM sense amplifier |
| Write architecture | Tri-state inverter write driver per column |
| Timing | Replica bitline generates self-timed SAE |
| Clocking | Two-phase non-overlapping internal clocks from one external CLK |
| Array choice | No column mux; all four addressed bits are read/written in parallel |
6T bitcell (CR = 2, PR = 1) — full sizing context is in the PDF.
All headline numbers below come from the LaTeX report and its cited SPICE evidence.
| Metric | Result |
|---|---|
Sustainable max CLK frequency fmax (W/W/R/R sweep) |
4.571 GHz (T_min = 218.75 ps = 0.21875 ns; find_fmax.py --json prints 4.571429 GHz before display rounding) |
Equivalent frequency feq = 1 / (CLK -> Dout) (single-edge latency; not sustained CLK) |
9.037 GHz (from f_eq_ghz in ngspice spice/top.spi Performance Metrics) |
Top-level CLK to Dout (single read access) |
110.65 ps (t_clk_to_dout ≈ 1.1065×10⁻¹⁰ s in the same block) |
| Frequency requirement | 500 MHz |
| Sustainable frequency margin | ~9.14× |
| Average top-level power (12 ns validation window, 500 MHz validation CLK) | 21.367 µW (`P = VDD × |
| Functional readback at 5 ns | 0x5 PASS |
| Functional readback at 7 ns | 0xA PASS |
Bitcell write 1 -> 0 |
9.87 ps |
Bitcell write 0 -> 1 |
21.8 ps |
| Read disturb maximum storage-node rise | 95.4 mV |
| Final FOM (access-time delay term) | ≈ 1.256×10⁻²² (60 × 8 × P × D² with P and D from the validation deck; see PDF §11) |
find_fmax.py on shipped top.spi: sustainable f_max 4.571 GHz, 0.21875 ns minimum period, ~9.14× vs 500 MHz, steady verify (e.g. 8 W/W/R/R macros / 32 CLK cycles) PASS. Re-run the script and refresh the PNG for a matching terminal capture — media/terminal/fmax.png.
Two distinct frequency claims—keep them in separate mental buckets:
fmax(sustained) ≈ 4.571 GHz atT_min= 218.75 ps comes from the cycle-stepped sweep inspice/find_fmax.py: binary search on CLK period with a W/W/R/R pattern each cycle, functional readback at 0.5 V, then optional steady verify (e.g. 8 macros / 32 CLK cycles in the saved transcript). Usepython3 spice/find_fmax.py --jsonforsustained_fmax_ghz(e.g. 4.571429 on the shipped deck).feq(latency-only) ≈ 9.037 GHz is1 / t_clk_to_doutfrom the.controlblock inspice/top.spiaftertranat the 500 MHz validation CLK. It is not a claim that the macro runs continuously at 9 GHz; it is the inverse of the measured single-edge CLK→Doutdelay (~110.65 ps) and feeds the FOM delay term.- Regression screening:
spice/parallel_cell_mix.pycan run many integer width-composed decks in parallel; on the current export, screened recipes reproduced the same ~4.57 GHz sustained closure, supporting that the limiter is a shared cycle envelope rather than a single cell tweak. Evidence: media/terminal/fmax.png (sustainedf_maxsweep + steady verify) and a freshngspice spice/top.spirun (Performance Metrics:t_clk_to_dout,iavg_vdd,pavg_mw,f_eq_ghz) or media/terminal/final-terminal-out.png (archived capture of the same deck).
To reproduce the sustained sweep with a nicer terminal harness (banner/spinner + JSON saved):
./scripts/run-find-fmax.shThe top level registers all inputs, decodes the 4-bit address into sixteen wordlines, activates four identical column slices, and uses a replica column to time the read decision.
Key architectural choices:
- 16x4 organization, no column mux: avoids a pass-gate mux in the read path and keeps bitline capacitance low for this small array.
- 6T bitcell: keeps the repeated area term low while meeting read stability and writeability targets with
CR = 2,PR = 1. - StrongARM sensing: provides fast regenerative readout without static sense-amp current.
- Replica timing: tracks real bitline discharge better than a fixed inverter-chain delay.
- Two-phase clocking: separates precharge from active wordline/write/sense windows to reduce contention.
Electric export; PNG flattened on white.
Screenshots of PDF figures live under media/readme/ as figN.png (printed Figure N in ESE3700_Proj2_Marhguy.pdf). Figure 1 is already at the top of this page; the full TikZ / methodology figures are in the report—below are only a couple of extras worth scrolling on GitHub.
Decoder / SA / write paths do not add to the bitcell-area FOM term—only the repeated 6T width does (§2 in the PDF).
Figure 38 — find_fmax.py sweep (fig:fmax_search)
Figure 43 — FOM sensitivity (fig:fom_sensitivity_bars)
| Fig | File |
|---|---|
| 2 — Report flow | fig2.png |
| 3 — FOM pipeline | fig3.png |
| 4 — Array organization | fig4.png |
| 39 — Read delay stack | fig39.png |
| 40 — Write delay stack | fig40.png |
| 42 — Energy split | fig42.png |
The PDF report contains the complete schematic set (column slice, precharge, sense amp, decoder, etc.). Top-level behavioral simulation:
Top-level validation: writes then reads 0x5 and 0xA.
| Path | Description |
|---|---|
| ESE3700_Proj2_Marhguy.tex | LaTeX source for the full report |
| ESE3700_Proj2_Marhguy.pdf | Compiled report PDF, produced by CI after a successful run |
| media/ | Figures, schematics, waveform PNGs, and terminal captures cited by the report |
| media/readme/ | README diagrams: figN.png = PDF Figure N (screenshots of report figures) |
| spice/ | SPICE netlists, Electric libraries, simulation helpers, and SVG waveform masters |
| spice/find_fmax.py | Cycle-scaled maximum-frequency sweep driver |
| .github/workflows/ | GitHub Actions workflow for building and committing the report PDF |
| scripts/ | Optional local helpers for CI-like LaTeX builds |
Requirements: a modern TeX distribution with latexmk, or Docker/Podman for the containerized helper script.
Native build:
latexmk -pdf -file-line-error -halt-on-error -interaction=nonstopmode ESE3700_Proj2_Marhguy.texContainerized build matching the GitHub Action:
./scripts/run-latex-ci-local.shThe local helper uses the same TeX Live container family as the CI workflow.
The LaTeX to PDF workflow is configured to run on pushes to main or master when the LaTeX source, figures, or workflow change. It compiles ESE3700_Proj2_Marhguy.tex and commits only ESE3700_Proj2_Marhguy.pdf back to the repository with [skip ci] in the commit message.
The workflow also supports manual workflow_dispatch, which is useful for the first PDF build after the repository is pushed. Until the workflow has run at least once on GitHub, the badge at the top may show no status.
The SPICE decks are exported from Electric VLSI and use a PTM-style 22 nm HP model card. Some decks may contain local .include paths from the author's machine; update those paths to your local 22nm_HP.pm before running simulations elsewhere.
Important entry points:
- spice/top.spi: top-level netlist and validation driver. The embedded
.controlblock prints the headlinet_clk_to_dout(single-edge access),iavg_vdd,pavg_mw, andf_eq_ghz = 1 / t_clk_to_doutused in the report. - spice/find_fmax.py: cycle-stepped
fmaxsweep driver. Binary-searches the CLK period under a 4-cycle write/write/read/read schedule against the livetop.spi; on the current deck closure isT_min = 218.75 ps(fmax ≈ 4.571 GHz). Run with--jsonfor metrics only on stdout. - spice/parallel_cell_mix.py: optional parallel driver for per-cell integer width scaling +
find_fmax.py(CSV logs) for regression screening. - spice/sram_6t_cell.spi: repeated 6T memory bitcell.
- spice/column_slice.spi: precharge, write driver, sense amp, and output latch integration.
- spice/replica_column.spi: dummy-column timing path for self-timed
SAE.
This work was completed in compliance with the University of Pennsylvania Code of Academic Integrity, as stated on the report title page. This repository is an archive of the author's own project materials and should not be treated as a substitute for any course submission process.
If you reuse figures, netlists, or excerpts for coursework or research, cite or link this repository and the course context appropriately. The authoritative technical narrative, assumptions, measurement conditions, and conclusions are in the PDF report.
Suggested GitHub topics: sram, vlsi, spice, latex, cmos, memory, 22nm, ese3700, upenn.
