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digital-circuit-simulation

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ammarmalik17 / Verilog_Adders

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This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.

circuit-simulation verilog-hdl test-bench half-adder hardware-description-language digital-electronics full-adder verilog-project vlsi-design rtl-design arithmetic-operations fpga-verilog logic-circuit-design behavioral-modeling 4-bit-adder verilog-adders gate-level-design dataflow-design digital-circuit-simulation hdl-coding
  • Updated Aug 24, 2024
  • Verilog

ginabisoondial / Simple-General-Purpose-Processor

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Designed and implemented a simple general-purpose processor using VHDL and Quartus 13.0. Developed latches, an FSM, a 4-to-16 decoder, and ALU components, then tested arithmetic, logic, and decision-making operations through waveform simulations and FPGA implementation.

fsm fpga decoder vhdl embedded-systems finite-state-machine digital-logic computer-architecture alu digital-circuit digital-circuits quartus vhdl-code digital-circuit-design hardware-design vhdl-language digital-circuit-simulator digital-circuit-simulation
  • Updated Sep 8, 2026
  • VHDL

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