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floating-point-substraction

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Manju7882 / IEEE-754-32-bit-Floating-Point-Subtraction-Verilog

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This project implements a single-precision IEEE-754 floating-point subtraction unit using Verilog HDL. It performs sign handling, exponent alignment, mantissa subtraction, and result normalization. The design is verified through simulation and is suitable for understanding basic FPU operation and digital arithmetic design.

digital verilog vlsi ieee754 floating-point-substraction rtl-design
  • Updated Jan 3, 2026
  • Verilog

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