An 8-bit CPU with a custom ISA, designed from scratch in Verilog, and its complete assembler toolchain developed in C++.

An open-source hardware simulator and live telemetry engine for generative AI. Track total system resource utilization in real-time across storage, memory paths, and compute blocks to eliminate black-box execution failures.

AI-assisted smart irrigation system combining ESP32 embedded hardware, multi-source power electronics, self-hosted cloud backend, MQTT communication, automation workflows, and context-aware decision logic validated in real-world operation.

Design and implementation of an ASIC with an 8051 microcontroller core. Includes VHDL modules, C applications, RTL simulations, and mixed-signal validation. Focused on hardware-software co-design and optimization.

Comprehensive survey of CNN hardware acceleration across FPGA, ASIC, and VLSI implementations spanning five real-world domains. Presents unified benchmarks, cross-domain optimisation strategies, and key research challenges for efficient, low-power, real-time AI systems; manuscript under review.

FPGA hardware acceleration projects using SystemVerilog, AXI, DMA, C drivers, pipelining, and parallel compute architectures.