Turing-Complete 8-bit CPU from 12K+ Logic Gates: Asymmetric 10-bit Addressing & 16-Level Call Stack with Full Toolchain – Solo Built by a 12-Year-Old in 12 days
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Updated
May 28, 2026
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nand-gates
Here are 3 public repositories matching this topic...
Connectome-constrained circuit synthesis: the fly giant-fiber escape reflex as exhaustively verified NAND/LATCH netlists
drosophila evm logic-synthesis connectome tapeout nand-gates differentiable-logic exhaustive-verification
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Sep 16, 2026 - HTML
Digital Design laboratory project exploring sequential logic circuits, including latches and flip-flops (RS, D, JK, T, Master-Slave), with interactive NI Multisim simulations and detailed documentation (Logic Design, UNIWA).
counter academic-project digital-design sequential-logic multisim logic-circuits flip-flops latches uniwa nand-gates memory-elements
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Updated
Feb 21, 2026
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