OpenTitan Rv Core Ibex IP block

System Reset Controller (sysrst_ctrl) that provides programmable hardware-level responses to trusted IOs and basic board-level reset sequencing capabilities

Entropy Distribution Network (EDN) interfaces to the CSRNG IP module

Keccak Message Authentication Code (KMAC) and Secure Hashing Algorithm 3 (SHA3)

Cryptographically Secure Random Number Generator (CSRNG)

OpenTitan Flash Ctrl IP block

OpenTitan UART IP - Full duplex serial communication peripheral with programmable baud rate, RX/TX buffers, and interrupt support

The mailbox IP block in the OpenTitan Integrated design implements a request-response channel that the host System-on-Chip (SoC) may use to request security ser

This document specifies the OTP MACRO hardware IP functionality.

ROM controller (rom_ctrl) is the connection between the chip and its ROM

Analog to Digital Converter Control Interface

SRAM memory controller

RISC-V Debug System wrapper functionality

Entropy Source: interface to an external physical random noise generator

Generic TL-UL to APB protocol adapter. Connects any APB peripheral to a TileLink Uncached Lightweight (TL-UL) crossbar for Ibex/OpenTitan RISC-V SoCs.

OpenTitan Keymgr Dpe IP block

The Direct Memory Access (DMA) controller is a peripheral within the OpenTitan system-on-chip (SoC).

OpenTitan Prim Xilinx Ultrascale IP block

:

I2C controller