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Project-4-SPI-Controller-Timing-Closure-and-Physical-Sign-off

PreethamSK163 / Project-4-SPI-Controller-Timing-Closure-and-Physical-Sign-off

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A hands-on implementation of physical design for a Serial Peripheral Interface (SPI) controller — progressing from RTL Verilog through synthesis, placement, static timing analysis, routing, DRC, LVS, and GDSII generation using the open-source Qflow EDA toolchain with OSU018 standard cell library.

yosys physical-design open-source-eda spi-controller qflow magic-vlsi rtl-to-gdsii osu018
  • Updated Apr 3, 2026

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