register-description-language

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SystemRDL / systemrdl-compiler

SystemRDL 2.0 language compiler front-end

asic fpga eda csr registers systemrdl register-descriptions systemrdl-compiler hardware-description-language design-automation register-description-language

Updated Sep 22, 2026
C++

Silicon1602 / srdl2sv

Star

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

asic fpga verilog rdl systemverilog hdl registers systemrdl systemrdl-compiler hardware-description-language register-description-language

Updated Nov 27, 2021
Python

Semantic compatibility analysis and configurable quality gates for SystemRDL specifications. Detects firmware-breaking register changes, produces CI reports and provides scalable exploration of large register maps.

asic fpga eda csr registers systemrdl register-descriptions systemrdl-compiler hardware-description-language design-automation register-description-language

Updated Jul 17, 2026
Python

taichi-ishitani / systemrdl

Sponsor

Star

SystemRDL front-end for Ruby

systemrdl register-descriptions register-description-language

Updated Sep 27, 2026
Ruby

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