Pong game on FPGA in VHDL with 640x480 @ 60 Hz VGA output, paddle physics, and collision detection. Xilinx Spartan-3E.
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Updated
May 14, 2026 - VHDL
Pong game on FPGA in VHDL with 640x480 @ 60 Hz VGA output, paddle physics, and collision detection. Xilinx Spartan-3E.
Direct-mapped cache controller with 7-state FSM and SDRAM interface in VHDL. Xilinx Spartan-3E.
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