Digital design project for a simple integer multiplier using Booth's multiplication algorithm made through ASM design method

This repository contains my custom finite state machine algorithms and their corresponding testbenches, generated using TerosHDL, for robust validation.

TerosHDL Documentation in Docusaurus

A reusable and configurable template for FPGA development projects using Verilog and Xilinx Vivado. This template is designed for the CMOD A7 FPGA board but can be easily adapted for other boards.