Convolution Neural Network Using FPGA

Overall design an FPGA implementation for convolutional neural networks where the FPGA serves as a hardware accelerator to speed up the required calculations in a convolutional network. Throughout the convolution an appropriate convolution kernel of a proper size is used which can be edited in the code.

What it contains?

• Max pooling
• Overall convolution
• Testbench

Language used

• Verilog

Tools used

• ModelSim
• Xilinix