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vanshikag1410/README.md

Oh! Now that you're here, I am ...

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Booting Vanshika_Gupta.v ...

👩‍💻 About

I'm fascinated by how ideas on a whiteboard eventually become working hardware.

From designing datapaths and control logic to implementing systems on FPGA, I enjoy exploring the journey from architecture to silicon.

⚡ Domains

  • Computer Architecture
  • RTL Design & Verification
  • FPGA Development
  • Digital Design
  • RISC-V Systems

🛠 Engineering Toolbox

Digital Design & Verification

VerilogSystemVerilogRTL DesignFPGA PrototypingVivado

Computer Architecture

RISC-V ArchitectureProcessor DesignDatapath DesignControl LogicHardware Acceleration

Software & Scripting

PythonC++MATLABSynopsys

🌱 Currently Exploring

ASIC Design FlowUVMTiming AnalysisPhysical Design

🚀 Featured Builds

⚙️ SoC Design & Integration

Experience with RISC-V based system design, hardware subsystems, and FPGA prototyping.

⚡ FPGA-Based Hardware Acceleration

Working on efficient hardware implementations for machine learning and signal-processing applications.

🧮 Arithmetic & Computing Architectures

Investigating alternative numerical representations and hardware accelerators for efficient computation.

⚙️ System Debug Log

[ Booting hardware_profile.v ]
> Favorite_ISA      : "RV32I"
> Last_Location     : "Following a rogue signal through three nested modules..."
> Exception_Caught  : "Missing connection. (Warning: infinite loop possible)"
> Natural_Habitat   : [ "RTL", "Waveforms", "Timing Reports" ]
> Current_Obsession : "Making hardware do more with less."
> Primary_Mission   : "Turning abstract specifications into breathing silicon."
[ Log execution complete. ]

🤝 Let's Connect

LinkedIn     Email     Resume

Pinned Loading

  1. fp32-to-posit32-hardware fp32-to-posit32-hardware Public

    Hardware implementation of IEEE-754 FP32 to Posit-32 conversion and Posit-32 multiplication, modeled in MATLAB and synthesized to Verilog using HDL Coder, with RTL simulation and FPGA synthesis in …

    Verilog

  2. Postman-Challenge Postman-Challenge Public

    Forked from Jisha-tr/Postman-Challenge

    This is the all in one place for documentation help regarding the postman challenge.

    JavaScript

  3. RISC_V RISC_V Public

    5-Stage Pipelined RISC-V Processor (RV32I)

    Verilog

  4. SpillT SpillT Public

    Java

  5. vanshikag1410 vanshikag1410 Public

    Config files for my GitHub profile.

  6. Hit3n-hi10/RV32I Hit3n-hi10/RV32I Public

    RV32I single core

    SystemVerilog 1