Update SysId step voltage guidance

[TLNing260310]

Summary

• update the documented SysId dynamic step-voltage default from 7 V to 4 V
• recommend starting with a lower mechanism-appropriate value and increasing it only when needed
• explain that excessive voltage can cause wheel slip and invalidate characterization data
• show explicit 4 V configuration in the Java and Python examples

Validation

• official doc8_redown.py lint on the changed page (0 errors)
• git diff --check

Companion documentation for wpilibsuite/allwpilib#9375 and wpilibsuite/allwpilib#7794.

[TLNing260310]

The Read the Docs preview failure is unrelated to this change. Its only fatal warning is an unresolved external Python class reference in source/docs/software/advanced-controls/controllers/trapezoidal-profiles.rst:26 (wpimath.TrapezoidProfile.Constraints). The changed creating-routine.rst page emitted no warnings, and the repository's doc8_redown.py lint passes with 0 errors. The GitHub Actions workflow is still awaiting maintainer approval for this fork PR.

[sciencewhiz]

How did you validate that the updated code samples work?

The unrelated build failure has been fixed in main, so it will pass if you merge/rebase with main.