Extend set of dslx_to_pipeline arguments#55
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Signed-off-by: Eryk Szpotanski <eszpotanski@antmicro.com>
Signed-off-by: Eryk Szpotanski <eszpotanski@antmicro.com>
Signed-off-by: Eryk Szpotanski <eszpotanski@antmicro.com>
Signed-off-by: Eryk Szpotanski <eszpotanski@antmicro.com>
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This PR adds following
dslx2pipelineargs:use_system_verilog,reset_active_low,reset_asynchronous.Moreover, it modifies the flow - instead of calling
dslx2pipeline, it is split into three stages:dslx2ir,ir2optandir2pipeline. This allows to specify the top from IR, enabling the codegen ofprocs.