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added Jenkinsfile to build and run test applications on ah05-sdram board #41

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73f7f92
change the TEST_LEVEL to default in jenkinsfile
alexyiuxmos Jul 16, 2026
782873b
added xcore_ai_sdram_test_board xn file
alexyiuxmos Jul 20, 2026
ca78559
updated the port settings
alexyiuxmos Jul 21, 2026
f327577
correct the Jenkins agent
alexyiuxmos Jul 21, 2026
baf5319
exit loop from multi client test
alexyiuxmos Jul 21, 2026
2cb04ec
exit loop for multi client
alexyiuxmos Jul 21, 2026
66a1f8f
updated Jenkinsfile
alexyiuxmos Jul 21, 2026
2d14068
update README.rst and CHANGLOG.rst
alexyiuxmos Jul 22, 2026
8f55eb5
fix typo errors
alexyiuxmos Jul 22, 2026
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5 changes: 5 additions & 0 deletions CHANGELOG.rst
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@@ -1,6 +1,11 @@
lib_sdram change log
====================

3.5.0
-----

* CHANGED: updated example and test to support AH05-SDRAM (xcore.ai)

3.4.0
-----

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167 changes: 111 additions & 56 deletions Jenkinsfile
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Expand Up @@ -36,80 +36,135 @@ pipeline {
}

stages {
stage('🏗️ Build and test') {
agent {
label 'x86_64 && linux && documentation'
}
stage ('Build Docs and Test') {
parallel {
stage('🏗️ Build doc') {
agent {
label 'x86_64 && linux && documentation'
}

stages {
stage('Checkout') {
steps {
stages {
stage('Checkout') {
steps {

println "Stage running on ${env.NODE_NAME}"
println "Stage running on ${env.NODE_NAME}"

script {
def (server, user, repo) = extractFromScmUrl()
env.REPO_NAME = repo
script {
def (server, user, repo) = extractFromScmUrl()
env.REPO_NAME = repo
}

dir(REPO_NAME){
checkoutScmShallow()
}
}
}

dir(REPO_NAME){
checkoutScmShallow()
stage('Examples build') {
steps {
dir("${REPO_NAME}/examples") {
xcoreBuild()
}
}
}
}
}

stage('Examples build') {
steps {
dir("${REPO_NAME}/examples") {
xcoreBuild()
stage('Repo checks') {
steps {
warnError("Repo checks failed")
{
runRepoChecks("${WORKSPACE}/${REPO_NAME}")
}
}
}
}
}

stage('Repo checks') {
steps {
warnError("Repo checks failed")
{
runRepoChecks("${WORKSPACE}/${REPO_NAME}")
stage('Doc build') {
steps {
dir(REPO_NAME) {
buildDocs()
}
}
}

stage("Archive sandbox") {
steps {
archiveSandbox(REPO_NAME)
}
}
}
} // build doc
stage('🏗️ Build and test') {
agent {
label 'ah05-sdram'
}
}

stage('Doc build') {
steps {
dir(REPO_NAME) {
buildDocs()
stages {
stage('Checkout') {
steps {

println "Stage running on ${env.NODE_NAME}"

script {
def (server, user, repo) = extractFromScmUrl()
env.REPO_NAME = repo
}

dir(REPO_NAME){
checkoutScmShallow()
}
}
}
}
}

stage('Tests') {
steps {
dir("${REPO_NAME}/tests") {
withTools(params.TOOLS_VERSION) {
createVenv(reqFile: "requirements.txt")
withVenv {
xcoreBuild(archiveBins: false)
// Use the TEST_LEVEL parameter to control the test coverage
runPytest("--level=${params.TEST_LEVEL}")

stage('Examples build') {
steps {
dir("${REPO_NAME}/examples") {
xcoreBuild()
}
}
}

stage('Repo checks') {
steps {
warnError("Repo checks failed")
{
runRepoChecks("${WORKSPACE}/${REPO_NAME}")
}
}
}
}
}

stage("Archive sandbox") {
steps {
archiveSandbox(REPO_NAME)
stage('Tests') {
steps {
echo "TEST_LEVEL: ${params.TEST_LEVEL}"
dir("${REPO_NAME}/tests") {
withTools(params.TOOLS_VERSION) {
createVenv(reqFile: "requirements.txt")
withVenv {
xcoreBuild(archiveBins: false)
dir("sdram_testbench") {
sh "xrun --io bin/sdram_testbench.xe"
}
dir("sdram_multi_client_test") {
sh "xrun --io bin/sdram_multi_client_test.xe"
}
}
}
}
}
}

stage("Archive sandbox") {
steps {
archiveSandbox(REPO_NAME)
}
}
} // stages
post {
cleanup {
xcoreCleanSandbox()
}
}
}
} // stages
post {
cleanup {
xcoreCleanSandbox()
}
}
} // stage 'Build and test'
} // stage 'build docs and test'
} // parallel
}

stage('🚀 Release') {
when {
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8 changes: 4 additions & 4 deletions README.rst
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Expand Up @@ -5,18 +5,18 @@ lib_sdram: SDRAM library
##############################

:vendor: XMOS
:version: 3.4.0
:version: 3.5.0
:scope: General Use
:description: SDRAM server and Memory address allocator components
:category: General Purpose
:keywords: Memory,SDRAM
:devices: xcore-200
:devices: xcore-200, xcore-ai

*******
Summary
*******

The XMOS SDRAM library is designed for read and write access of arbitrary length 32b long word buffers at up to 62.5MHz clock rates.
The XMOS SDRAM library is designed for read and write access of arbitrary length 32b long word buffers at up to 60.0MHz clock rates.
It uses an optimized pinout with address and data lines overlaid along with other pinout
optimizations to implement 16 bit read/writes to Single Data Rate (SDR) SDRAM devices of size up to 256Mb,
while consuming a total of just 20 xCORE I/O pins.
Expand All @@ -27,7 +27,7 @@ Features

* Configurability of:
* SDRAM capacity
* clock rate (62.5 to 25MHz steps are provided)
* clock rate (60.0 to 30MHz steps are provided)
* refresh properties
* Supports:
* read of 32b long words
Expand Down
4 changes: 3 additions & 1 deletion examples/app_sdram_demo/CMakeLists.txt
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Expand Up @@ -2,7 +2,9 @@ cmake_minimum_required(VERSION 3.21)
include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake)
project(sdram_demo)

set(APP_HW_TARGET SLICEKIT-XC200-X1.xn)
# set(APP_HW_TARGET SLICEKIT-XC200-X1.xn)
set(APP_HW_TARGET xcore_ai_sdram_test_board.xn)
set(APP_XSCOPE_SRCS "")

set(APP_DEPENDENT_MODULES "lib_sdram")
set(APP_COMPILER_FLAGS -g -O2)
Expand Down
16 changes: 9 additions & 7 deletions examples/app_sdram_demo/src/sdram_demo.xc
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Expand Up @@ -9,7 +9,8 @@
//For XS2 (xCORE200) put an SDRAM slice into the 'triangle' slot of tile 0 of the XP-SKC-X200 slice kit
//If using 256Mb slice, then define USE_256Mb below, otherwise leave commented out

#define USE_256Mb 1 //Else will assume 64Mb
#define USE_256Mb 0//1 //Else will assume 64Mb
#define JTAG_TO_PRINT 1

void application(streaming chanend c_server) {
#define BUF_WORDS (16)
Expand Down Expand Up @@ -76,14 +77,14 @@ on tile[SERVER_TILE] : out buffered port:8 sdram_we = XS1_
on tile[SERVER_TILE] : out port sdram_clk = XS1_PORT_1L;
on tile[SERVER_TILE] : clock sdram_cb = XS1_CLKBLK_2;
#else
//Square slot on A16 slicekit
//Uses IS42S16400D 64Mb part supplied on AH05_SDRAM board
#define SERVER_TILE 1
on tile[SERVER_TILE] : out buffered port:32 sdram_dq_ah = XS1_PORT_16A;
on tile[SERVER_TILE] : out buffered port:32 sdram_cas = XS1_PORT_1B;
on tile[SERVER_TILE] : out buffered port:32 sdram_ras = XS1_PORT_1G;
on tile[SERVER_TILE] : out buffered port:8 sdram_we = XS1_PORT_1C;
on tile[SERVER_TILE] : out buffered port:32 sdram_cas = XS1_PORT_1A;
on tile[SERVER_TILE] : out buffered port:32 sdram_ras = XS1_PORT_1P;
on tile[SERVER_TILE] : out buffered port:8 sdram_we = XS1_PORT_1M;
on tile[SERVER_TILE] : out port sdram_clk = XS1_PORT_1F;
on tile[SERVER_TILE] : clock sdram_cb = XS1_CLKBLK_2;
on tile[SERVER_TILE] : clock sdram_cb = XS1_CLKBLK_1;
#endif

int main() {
Expand All @@ -99,7 +100,8 @@ int main() {
#if USE_256Mb
2, 256, 16, 9, 13, 2, 64, 8192, 4); //IS45S16160D 256Mb option or similar
#else
2, 128, 16, 8, 12, 2, 64, 4096, 4); //Uses IS42S16400D 64Mb part supplied on SDRAM slice
// 2, 128, 16, 8, 12, 2, 64, 4096, 4); //Uses IS42S16400D 64Mb part supplied on SDRAM slice
2, 128, 16, 8, 12, 2, 64, 4096, 5); //Uses IS42S16400D 64Mb part supplied on AH05_SDRAM board
#endif
//Note clock div 4 gives (500/ (4*2)) = 62.5MHz

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55 changes: 55 additions & 0 deletions examples/app_sdram_demo/xcore_ai_sdram_test_board.xn
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@@ -0,0 +1,55 @@
<?xml version="1.0" encoding="UTF-8"?>
<Network xmlns="http://www.xmos.com"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.xmos.com http://www.xmos.com">
<Type>Board</Type>
<Name>xcore-ai SDRAM Test Board</Name>

<Declarations>
<Declaration>tileref tile[2]</Declaration>
</Declarations>

<Packages>
<Package id="0" Type="XS3-UnA-1024-FB265">
<Nodes>
<Node Id="0" InPackageId="0" Type="XS3-L16A-1024" Oscillator="24MHz" SystemFrequency="600MHz" ReferenceFrequency="100MHz">
<Boot>
<Source Location="SPI:bootFlash" />
</Boot>
<Tile Number="0" Reference="tile[0]">
<!-- XUD Ports -->
<Port Location="XS1_PORT_1H" Name="PORT_USB_TX_READYIN"/>
<Port Location="XS1_PORT_1J" Name="PORT_USB_CLK"/>
<Port Location="XS1_PORT_1K" Name="PORT_USB_TX_READYOUT"/>
<Port Location="XS1_PORT_1I" Name="PORT_USB_RX_READY"/>
<Port Location="XS1_PORT_1E" Name="PORT_USB_FLAG0"/>
<Port Location="XS1_PORT_1F" Name="PORT_USB_FLAG1"/>
<Port Location="XS1_PORT_8A" Name="PORT_USB_TXD"/>
<Port Location="XS1_PORT_8B" Name="PORT_USB_RXD"/>
<!-- SPI Ports -->
<Port Location="XS1_PORT_1A" Name="PORT_SPI_MISO"/>
<Port Location="XS1_PORT_1B" Name="PORT_SPI_SS"/>
<Port Location="XS1_PORT_1C" Name="PORT_SPI_CLK"/>
<Port Location="XS1_PORT_1D" Name="PORT_SPI_MOSI"/>
</Tile>
<Tile Number="1" Reference="tile[1]">
</Tile>
</Node>
</Nodes>
</Package>
</Packages>

<ExternalDevices>
<Device NodeId="0" Tile="0" Name="bootFlash" Class="SPIFlash" Type="AT25SF161">
<Attribute Name="PORT_SPI_MISO" Value="PORT_SPI_MISO" />
<Attribute Name="PORT_SPI_SS" Value="PORT_SPI_SS" />
<Attribute Name="PORT_SPI_CLK" Value="PORT_SPI_CLK" />
<Attribute Name="PORT_SPI_MOSI" Value="PORT_SPI_MOSI" />
</Device>
</ExternalDevices>

<JTAGChain>
<JTAGDevice NodeId="0"/>
</JTAGChain>

</Network>
4 changes: 2 additions & 2 deletions lib_sdram/lib_build_info.cmake
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@@ -1,5 +1,5 @@
set(LIB_NAME lib_sdram)
set(LIB_VERSION 3.4.0)
set(LIB_VERSION 3.5.0)
set(LIB_INCLUDES api src)

set(LIB_DEPENDENT_MODULES "")
Expand All @@ -10,4 +10,4 @@ set(LIB_COMPILER_FLAGS -O3
-fcomment-asm
-g)

XMOS_REGISTER_MODULE()
XMOS_REGISTER_MODULE()
6 changes: 3 additions & 3 deletions lib_sdram/src/io.S
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@@ -1,7 +1,7 @@
// Copyright 2014-2026 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
.text
#ifdef __XS2A__
#if defined (__XS2A__) || defined (__XS3A__)
//xCore 200 optimised version with support for >8bit row addresses
.cc_top sdram_block_write.function
.align 4
Expand Down Expand Up @@ -202,7 +202,7 @@ sdram_block_read:
//r2 t0 - start time
//r3 word_count
//sp[1] row_words
//sp[2] cas_latency
//sp[2] read_time_offset

#define ras r0
#define dq_ah r1
Expand Down Expand Up @@ -339,7 +339,7 @@ sdram_block_read:
ldaw temp, r0[-temp]
set dp, temp

ldw temp, sp[READ_STACK_WORDS+2] //cas_latency
ldw temp, sp[READ_STACK_WORDS+2] //read_time_offset
add start_time, r2, temp

//calculate the time to issue the terminate cmd
Expand Down
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