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Add abi_riscv64.h with SAVE_GPR/SAVE_FPR macros for saving and restoring the RISC-V callee-saved registers, following the pattern established by the other abi_*.h headers. Refactor asm_riscv64.s (cgo crosscall2), asm_riscv64.s (runtime _rt0_riscv64_lib), and race_riscv64.s (racecallbackthunk) to use the new macros, replacing inline register save/restore sequences. Change-Id: I83cef17a35c57fc8b5e045e7181460283ae5b423 Reviewed-on: https://go-review.googlesource.com/c/go/+/749900 Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Quim Muntal <quimmuntal@gmail.com> Reviewed-by: Russ Cox <rsc@golang.org>
This CL implements hardware frame pointer support for riscv64. The stack layout is similar to arm64, but with the following specifics: - The FP register points to SP+8. - The return address (LR) is stored at SP. - The caller's FP is stored at SP-8. Change-Id: I3bc7af2abb024ea0b0e3432ed517641c6707f7a2
This reverts commit f2dc8bf.
This reverts commit 30aaed2.
This reverts commit edf59e9.
This reverts commit 0a0677b.
This reverts commit 61a1a48.
This reverts commit 91dafedbac6c7c78531d7001c8d55961287d91b1.
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